circuitspedia.com

VLSI (Part 2) nMOS fabrication Online test

Share this

0%
Created on

VLSI

VLSI (PART 2) nMOS fabrication

tail spin
In nMOS device, the gate material could be metal or polysilicon. This polysilicon layer has heavily doped polysilicon deposited by CVD.

1 / 26

1. In nMOS device, gate material could be

Designers must simulate multiple fabrication process or use system level technique for dealing with effects of variation.

2 / 26

2. .....................is used to deal with effect of variation.

Above a layer of silicon dioxide which acts as a barrier, an insulating layer is provided upon which other layers may be deposited and patterned.

3 / 26

3. What kind of substrate is provided above the barrier to dopants?

4 / 26

4. .................. architecture is used to design VLSI.

5 / 26

5. Heavily doped polysilicon is deposited using...............

Contact cuts are made in the desired polysilicon area, source and gate. COntact cuts are those places where connection has to be made.

6 / 26

6.  Contact cuts are made in...............

Very large scale integration is the process of creating an integrated circuit with thousands of transistors into one single chip.

7 / 26

7. VLSI technology uses ......................... to form integrated circuit.

Diffusion is carried out by heating the wafer to high temperature and passing a gas containing the desired ntype impurity.

8 / 26

8.  In diffusion process ................... impurity is desired.

In nMOS fabrication, etching is done using hydrofluoric acid or plasma. Etching is a process used to remove layers from the surface.

9 / 26

9. In nMOS fabrication, etching is done using

Problem statement is a high level representation of the system. Performance, functionality and physical dimensions are considered here.

10 / 26

10. Which is the high level representation of VLSI design?

Small scale integration has one or more logic gate. Further improved technology is medium scale integration which consists of hundred logic gates. Large scale integration has thousand logic gates.

11 / 26

11. Medium scale integration has ...............

In nMOS device, the gate material could be metal or polysilicon. This polysilicon layer has heavily doped polysilicon deposited by CVD.

12 / 26

12. In nMOS device, gate material could be ..............

13 / 26

13. The photoresist layer is exposed to...........

p impurities are introduced as the crystal is grown. This increases the hole concentration in the device.

14 / 26

14. ................impurities are added to the wafer of the crystal.

As photolithography comes closer to the fundamental law of optics, achieving high accuracy in doping concentration becomes difficult, which leads to error due to variation.

15 / 26

15. The difficulty in achieving high doping concentration leads to....................

Gate minimization technique is used to find the simplest, smallest and effective implementation of the logic.

16 / 26

16. Gate minimization technique is used to simplify the logic.

As the die size shrinks due to scaling, the number of die per wafer increases and the complexity of making the photomasks increases rapidly.

17 / 26

17.  As die size shrinks, the complexity of making the photomasks ...................

SIlicon-di-oxide is a very good insulator so a very thin layer is required in the fabrication of MOS transistor.

18 / 26

18. SIlicon-di-oxide is a good insulator.

The metal layer is masked and etched to form interconnection pattern. The metal layer was formed using aluminium deposited over the formed surface.

19 / 26

19. Interconnection pattern is made on..................

First in first out (FIFO) technique and finite state machine technique is used in the logic design of the VLSI circuits.

20 / 26

20. ..................... is used in logic design of VLSI.

Transistor-transistor logic offers higher integration density and it became the first integrated circuit revolution.

21 / 26

21. Which provides higher integration density?

22 / 26

22. Which is the commonly used bulk substrate in nMOS fabrication?

Aluminium is the suitable material used for the circuit interconnection or connecting two layers.

23 / 26

23. Which is used for the interconnection?

24 / 26

24. Physical and electrical specification is given in  ...................

Boron is used to suppress the unwanted conduction between transistor sites. It is implanted in the exposed regions.

25 / 26

25. ......................is used to suppress unwanted conduction.

Explanation: nMOS fabrication process is carried out in thin wafer of a single crystal with high purity.

26 / 26

26. nMOS fabrication process is carried out in

Your score is

The average score is 3%

0%

Share this

Leave a Comment

Your email address will not be published. Required fields are marked *