VLSI (Part 2) nMOS fabrication Online test

First in first out (FIFO) technique and finite state machine technique is used in the logic design of the VLSI circuits.

Transistor-transistor logic offers higher integration density and it became the first integrated circuit revolution.

Very large scale integration is the process of creating an integrated circuit with thousands of transistors into one single chip.

p impurities are introduced as the crystal is grown. This increases the hole concentration in the device.

As the die size shrinks due to scaling, the number of die per wafer increases and the complexity of making the photomasks increases rapidly.

Above a layer of silicon dioxide which acts as a barrier, an insulating layer is provided upon which other layers may be deposited and patterned.

SIlicon-di-oxide is a very good insulator so a very thin layer is required in the fabrication of MOS transistor.

Contact cuts are made in the desired polysilicon area, source and gate. COntact cuts are those places where connection has to be made.

Aluminium is the suitable material used for the circuit interconnection or connecting two layers.

As photolithography comes closer to the fundamental law of optics, achieving high accuracy in doping concentration becomes difficult, which leads to error due to variation.

Small scale integration has one or more logic gate. Further improved technology is medium scale integration which consists of hundred logic gates. Large scale integration has thousand logic gates.

Designers must simulate multiple fabrication process or use system level technique for dealing with effects of variation.

In nMOS fabrication, etching is done using hydrofluoric acid or plasma. Etching is a process used to remove layers from the surface.

Diffusion is carried out by heating the wafer to high temperature and passing a gas containing the desired ntype impurity.

Gate minimization technique is used to find the simplest, smallest and effective implementation of the logic.

Explanation: nMOS fabrication process is carried out in thin wafer of a single crystal with high purity.

Boron is used to suppress the unwanted conduction between transistor sites. It is implanted in the exposed regions.

Problem statement is a high level representation of the system. Performance, functionality and physical dimensions are considered here.

The metal layer is masked and etched to form interconnection pattern. The metal layer was formed using aluminium deposited over the formed surface.