HomeElectronics Multiple choice question MCQ online testVLSI online test mcq (part1) VLSI online test mcq (part1) Leave a Comment / Electronics Multiple choice question MCQ online test Spread the love 0% Created on July 23, 2023VLSI VLSI (part1) 1 / 50 The BiCMOS are preferred over CMOS due to . . . . . . . . a. Switching speed is more compared to CMOS b. Sensitivity is less with respect to the load capacitance c. High current drive capability d. All of the mentioned 2 / 50 In nMOS inverter configuration depletion mode device is called as . . . . . . . a. Pull down b. Pull up c. None of the mentioned d. All of the mentioned 3 / 50 What are the advantages of BiCMOS? a. Higher gain b. All of the mentioned c. Better noise characteristics d. High frequency characteristics 4 / 50 Substrate bias voltage is positive for nMOS. a. True b. False 5 / 50 If both the transistors are in saturation, then they act as . . . . . . . . a. Voltage source b. Current source c. Divider d. Buffer 6 / 50 In CMOS inverter, transistor is a switch having . . . . . . . . a. Infinite off resistance b. Buffer c. Finite off resistance d. Infinite on resistance 7 / 50 Speed power product is measured as the product of . . . . . . . . a. Gate power dissipation and absorption b. Gate switching delay and net gate power c. Gate switching delay and gate power absorption d. Gate switching delay and gate power dissipation 8 / 50 In CMOS fabrication, the photoresist layer is exposed to . . . . . . . . a. Fluorescent b. Infra red light c. Visible light d. Ultraviolet light 9 / 50 Which has better I/A? a. CMOS b. nMOS c. pMOS d. Bipolar 10 / 50 The . . . . . . . . is used to reduce the resistivity of poly silicon. a. Photo resist b. Doping impurities c. None of the mentioned d. Etching 11 / 50 The transistors used in BiCMOS are . . . . . . . . a. BJT b. Both BJT and MOSFETs c. JFET d. MOSFET 12 / 50 Substrate doping level should be decreased to avoid the latch-up effect. a. False b. True 13 / 50 Heavily doped polysilicon is deposited using . . . . . . a. Chemical vapour deposition b. Chemical vapour decomposition c. Chemical deposition d. Dry deposition 14 / 50 Surface mobility depends on . . . . . . . . a. Channel length b. Effective gate voltage c. Effective drain voltage d. Effective source voltage 15 / 50 BiCMOS inverter requires high load current sourcing a. True b. False 16 / 50 Ids depends on . . . . . . . a. Vss b. Vg c. Vds d. Vdd 17 / 50 What is the disadvantage of the MOS device? a. Limited voltage sinking b. Limited voltage sourcing c. Unlimited current sinking d. Limited current sourcing 18 / 50 Pass transistors are transistors used as . . . . . . . a. Switches connected in series b. Inverters used in series c. Switches connected in parallel d. Inverter used in parallel 19 / 50 Increasing fan-out . . . . . . . . the propagation delay. a. Increases b. Does not affect c. Decreases d. Exponentially decreases 20 / 50 The MOSFETS are arranged in this configuration to provide . . . . . . . . a. Zero static power dissipation b. High Input impedance c. Both zero static power dissipation and high input impedance d. None of the mentioned 21 / 50 For depletion mode transistor, gate should be connected to . . . . . . . . a. Drain b. Ground c. Source d. Positive voltage rail 22 / 50 What is the condition for non conducting mode? a. Vgs lesser than Vds b. Vgs = Vds = 0 c. Vds lesser than Vgs d. Vgs = Vds = Vs = 0 23 / 50 CMOS technology is used in developing which of the following? a. All of the mentioned b. Microcontrollers c. Digital logic circuits d. Microprocessors 24 / 50 If the gate is given sufficiently large charge, electrons will be attracted to . . . . . . a. Switch region b. Bulk region c. Drain region d. Channel region 25 / 50 Fast gate can be built by keeping . . . . . . . . a. High on resistance b. High output capacitance c. Input capacitance does not affect speed of the gate d. Low output capacitance 26 / 50 In BiCMOS, MOS switches are used to . . . . . . a. Drive input loads b. To amplify the input voltage c. To perform logic functions d. Drive output loads 27 / 50 As die size shrinks, the complexity of making the photomasks . . . . . . . a. Decreases b. Cannot be determined c. Increases d. Remains the same 28 / 50 The current Ids . . . . . . . . as Vds increases. a. Increases b. Remains fairly constant c. Decreases d. Exponentially increases 29 / 50 The n-well collector is formed by . . . . . . . a. Lightly doped n-type epitaxial layer on p-Substrate b. Heavily doped n-type epitaxial layer on p-Substrate c. Heavily doped n-type diffused layer on p-Substrate d. Lightly doped n-type diffused layer on p-Substrate 30 / 50 Interconnection pattern is made on . . . . . . a. Polysilicon layer b. Diffusion layer c. Silicon-di-oxide layer d. Metal layer 31 / 50 If p-transistor is conducting and has small voltage between source and drain, then it is said to work in . .. . . a. Linear region b. Saturation region c. Non saturation resistive region d. Cut-off region 32 / 50 Transconductance gives the relationship between . . . . . . . a. Output current and input voltage b. Input current and output voltage c. Input current and input voltage d. Output current and output voltage 33 / 50 Latch-up is the generation of . . . . . . . a. Low impedance path b. Low resistance path c. High resistance path d. High impedance path 34 / 50 Increasing the transconductance . . . . . . a. Decrease in output capacitance b. Decreasing input capacitance c. Increases input capacitance d. Decreasing area occupied 35 / 50 The isolated active areas are created by technique known as . . . . . . a. Etched field-oxide isolation or Local Oxidation of Silicon b. None of the mentioned c. Etched field-oxide isolation d. Local Oxidation of Silicon 36 / 50 In latch-up condition, parasitic component gives rise to . . . . . . . . conducting path. a. High capacitance b. High resistance c. Low resistance d. Low capacitance 37 / 50 MOS transistor structure is . . . . . . a. Symmetrical b. Non symmetrical c. Pseudo symmetrical d. Semi symmetrical 38 / 50 Switching speed of a MOS device depends on . . . . . . a. All of the mentioned b. Length channel c. Carrier mobility d. Gate voltage above a threshold 39 / 50 Which of the following is true when inputs are controlled by equal amounts of charge? a. Cg(MOS) lesser than Cbase(bipolar) b. Cg(MOS) greater than Cbase(bipolar) c. Cg(MOS) = Cbase(bipolar) d. Cs(MOS) lesser than Cbase(bipolar) 40 / 50 N-well is formed by . . . . . . . . a. Diffusion b. Filtering c. Dispersion d. Decomposition 41 / 50 Positive photo resists are used more than negative photo resists because . . . . . . . . a. Negative photo resists are less sensitive to light b. Positive photo resists are less sensitive to light c. Negative photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the positive photo resists d. Positive photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the negative photo resists 42 / 50 Which process produces a circuit which is less prone to latch-up effect? a. nMOS b. BiCMOS c. CMOS d. pMOS 43 / 50 Increasing Vsb . . . . . . . . the threshold voltage. a. Decreases b. Increases c. Does not effect d. Exponentially increases 44 / 50 Depletion mode MOSFETs are more commonly used as . . . . . . . . a. Buffers b. Resistors c. Switches d. Capacitors 45 / 50 In nMOS fabrication, etching is done using . . . . . . . . . a. Sulphuric acid b. Sodium chloride c. Plasma d. Hydrochloric acid 46 / 50 What are the advantages of E-beam masks? a. Complex design b. Larger feature size c. Looser layer d. Small feature size 47 / 50 Which is used for the interconnection? a. Aluminium b. Oxygen c. Boron d. Silicon 48 / 50 The dopants are introduced in the active areas of silicon by using which process? a. Diffusion process b. Chemical Vapour Deposition c. Either Diffusion or Ion Implantation Process d. Ion Implantation process 49 / 50 Contact cuts are made in . . . . . . . . . a. Drain b. Source c. Diffusion layer d. Metal layer 50 / 50 Surface mobility depends on . . a. Effective gate voltage b. Effective source voltage c. Channel length d. Effective drain voltage Your score is LinkedIn Facebook VKontakte 0% Restart quiz Exit Anonymous feedback Thank you Send feedback Spread the love
