HomeElectronics Multiple choice question MCQ online testVLSI online test mcq (part1) VLSI online test mcq (part1) Leave a Comment / Electronics Multiple choice question MCQ online test Spread the love 0% Created on July 23, 2023VLSI VLSI (part1) 1 / 50 The BiCMOS are preferred over CMOS due to . . . . . . . . a. High current drive capability b. All of the mentioned c. Sensitivity is less with respect to the load capacitance d. Switching speed is more compared to CMOS 2 / 50 In nMOS inverter configuration depletion mode device is called as . . . . . . . a. Pull up b. All of the mentioned c. None of the mentioned d. Pull down 3 / 50 What are the advantages of BiCMOS? a. High frequency characteristics b. All of the mentioned c. Better noise characteristics d. Higher gain 4 / 50 Substrate bias voltage is positive for nMOS. a. True b. False 5 / 50 If both the transistors are in saturation, then they act as . . . . . . . . a. Current source b. Buffer c. Divider d. Voltage source 6 / 50 In CMOS inverter, transistor is a switch having . . . . . . . . a. Infinite on resistance b. Buffer c. Finite off resistance d. Infinite off resistance 7 / 50 Speed power product is measured as the product of . . . . . . . . a. Gate switching delay and net gate power b. Gate power dissipation and absorption c. Gate switching delay and gate power absorption d. Gate switching delay and gate power dissipation 8 / 50 In CMOS fabrication, the photoresist layer is exposed to . . . . . . . . a. Infra red light b. Ultraviolet light c. Fluorescent d. Visible light 9 / 50 Which has better I/A? a. nMOS b. pMOS c. CMOS d. Bipolar 10 / 50 The . . . . . . . . is used to reduce the resistivity of poly silicon. a. None of the mentioned b. Photo resist c. Etching d. Doping impurities 11 / 50 The transistors used in BiCMOS are . . . . . . . . a. MOSFET b. BJT c. Both BJT and MOSFETs d. JFET 12 / 50 Substrate doping level should be decreased to avoid the latch-up effect. a. False b. True 13 / 50 Heavily doped polysilicon is deposited using . . . . . . a. Chemical deposition b. Dry deposition c. Chemical vapour deposition d. Chemical vapour decomposition 14 / 50 Surface mobility depends on . . . . . . . . a. Effective gate voltage b. Channel length c. Effective drain voltage d. Effective source voltage 15 / 50 BiCMOS inverter requires high load current sourcing a. True b. False 16 / 50 Ids depends on . . . . . . . a. Vss b. Vdd c. Vg d. Vds 17 / 50 What is the disadvantage of the MOS device? a. Unlimited current sinking b. Limited current sourcing c. Limited voltage sinking d. Limited voltage sourcing 18 / 50 Pass transistors are transistors used as . . . . . . . a. Switches connected in parallel b. Inverters used in series c. Inverter used in parallel d. Switches connected in series 19 / 50 Increasing fan-out . . . . . . . . the propagation delay. a. Does not affect b. Decreases c. Increases d. Exponentially decreases 20 / 50 The MOSFETS are arranged in this configuration to provide . . . . . . . . a. Zero static power dissipation b. Both zero static power dissipation and high input impedance c. None of the mentioned d. High Input impedance 21 / 50 For depletion mode transistor, gate should be connected to . . . . . . . . a. Source b. Positive voltage rail c. Ground d. Drain 22 / 50 What is the condition for non conducting mode? a. Vds lesser than Vgs b. Vgs lesser than Vds c. Vgs = Vds = 0 d. Vgs = Vds = Vs = 0 23 / 50 CMOS technology is used in developing which of the following? a. Microprocessors b. All of the mentioned c. Microcontrollers d. Digital logic circuits 24 / 50 If the gate is given sufficiently large charge, electrons will be attracted to . . . . . . a. Bulk region b. Channel region c. Drain region d. Switch region 25 / 50 Fast gate can be built by keeping . . . . . . . . a. Input capacitance does not affect speed of the gate b. High output capacitance c. High on resistance d. Low output capacitance 26 / 50 In BiCMOS, MOS switches are used to . . . . . . a. To perform logic functions b. To amplify the input voltage c. Drive output loads d. Drive input loads 27 / 50 As die size shrinks, the complexity of making the photomasks . . . . . . . a. Cannot be determined b. Remains the same c. Increases d. Decreases 28 / 50 The current Ids . . . . . . . . as Vds increases. a. Remains fairly constant b. Increases c. Exponentially increases d. Decreases 29 / 50 The n-well collector is formed by . . . . . . . a. Heavily doped n-type epitaxial layer on p-Substrate b. Lightly doped n-type epitaxial layer on p-Substrate c. Heavily doped n-type diffused layer on p-Substrate d. Lightly doped n-type diffused layer on p-Substrate 30 / 50 Interconnection pattern is made on . . . . . . a. Metal layer b. Diffusion layer c. Polysilicon layer d. Silicon-di-oxide layer 31 / 50 If p-transistor is conducting and has small voltage between source and drain, then it is said to work in . .. . . a. Saturation region b. Non saturation resistive region c. Linear region d. Cut-off region 32 / 50 Transconductance gives the relationship between . . . . . . . a. Input current and output voltage b. Output current and input voltage c. Output current and output voltage d. Input current and input voltage 33 / 50 Latch-up is the generation of . . . . . . . a. Low impedance path b. Low resistance path c. High resistance path d. High impedance path 34 / 50 Increasing the transconductance . . . . . . a. Decreasing input capacitance b. Increases input capacitance c. Decreasing area occupied d. Decrease in output capacitance 35 / 50 The isolated active areas are created by technique known as . . . . . . a. Etched field-oxide isolation b. Etched field-oxide isolation or Local Oxidation of Silicon c. Local Oxidation of Silicon d. None of the mentioned 36 / 50 In latch-up condition, parasitic component gives rise to . . . . . . . . conducting path. a. Low capacitance b. Low resistance c. High capacitance d. High resistance 37 / 50 MOS transistor structure is . . . . . . a. Non symmetrical b. Pseudo symmetrical c. Symmetrical d. Semi symmetrical 38 / 50 Switching speed of a MOS device depends on . . . . . . a. All of the mentioned b. Carrier mobility c. Gate voltage above a threshold d. Length channel 39 / 50 Which of the following is true when inputs are controlled by equal amounts of charge? a. Cg(MOS) greater than Cbase(bipolar) b. Cs(MOS) lesser than Cbase(bipolar) c. Cg(MOS) lesser than Cbase(bipolar) d. Cg(MOS) = Cbase(bipolar) 40 / 50 N-well is formed by . . . . . . . . a. Diffusion b. Filtering c. Decomposition d. Dispersion 41 / 50 Positive photo resists are used more than negative photo resists because . . . . . . . . a. Negative photo resists are less sensitive to light b. Positive photo resists are less sensitive to light c. Negative photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the positive photo resists d. Positive photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the negative photo resists 42 / 50 Which process produces a circuit which is less prone to latch-up effect? a. nMOS b. pMOS c. CMOS d. BiCMOS 43 / 50 Increasing Vsb . . . . . . . . the threshold voltage. a. Increases b. Exponentially increases c. Does not effect d. Decreases 44 / 50 Depletion mode MOSFETs are more commonly used as . . . . . . . . a. Switches b. Buffers c. Capacitors d. Resistors 45 / 50 In nMOS fabrication, etching is done using . . . . . . . . . a. Sulphuric acid b. Sodium chloride c. Hydrochloric acid d. Plasma 46 / 50 What are the advantages of E-beam masks? a. Larger feature size b. Complex design c. Small feature size d. Looser layer 47 / 50 Which is used for the interconnection? a. Oxygen b. Boron c. Silicon d. Aluminium 48 / 50 The dopants are introduced in the active areas of silicon by using which process? a. Ion Implantation process b. Diffusion process c. Chemical Vapour Deposition d. Either Diffusion or Ion Implantation Process 49 / 50 Contact cuts are made in . . . . . . . . . a. Metal layer b. Drain c. Diffusion layer d. Source 50 / 50 Surface mobility depends on . . a. Effective drain voltage b. Channel length c. Effective gate voltage d. Effective source voltage Your score is LinkedIn Facebook VKontakte 0% Restart quiz Exit Anonymous feedback Thank you Send feedback Spread the love
