HomeElectronics Multiple choice question MCQ online testVLSI online test mcq (part1) VLSI online test mcq (part1) Leave a Comment / Electronics Multiple choice question MCQ online test Spread the love 0% Created on July 23, 2023VLSI VLSI (part1) 1 / 50 The BiCMOS are preferred over CMOS due to . . . . . . . . a. All of the mentioned b. Switching speed is more compared to CMOS c. High current drive capability d. Sensitivity is less with respect to the load capacitance 2 / 50 In nMOS inverter configuration depletion mode device is called as . . . . . . . a. None of the mentioned b. All of the mentioned c. Pull down d. Pull up 3 / 50 What are the advantages of BiCMOS? a. High frequency characteristics b. Better noise characteristics c. All of the mentioned d. Higher gain 4 / 50 Substrate bias voltage is positive for nMOS. a. False b. True 5 / 50 If both the transistors are in saturation, then they act as . . . . . . . . a. Buffer b. Divider c. Voltage source d. Current source 6 / 50 In CMOS inverter, transistor is a switch having . . . . . . . . a. Infinite on resistance b. Buffer c. Infinite off resistance d. Finite off resistance 7 / 50 Speed power product is measured as the product of . . . . . . . . a. Gate switching delay and gate power absorption b. Gate switching delay and gate power dissipation c. Gate switching delay and net gate power d. Gate power dissipation and absorption 8 / 50 In CMOS fabrication, the photoresist layer is exposed to . . . . . . . . a. Fluorescent b. Infra red light c. Ultraviolet light d. Visible light 9 / 50 Which has better I/A? a. CMOS b. nMOS c. pMOS d. Bipolar 10 / 50 The . . . . . . . . is used to reduce the resistivity of poly silicon. a. Etching b. None of the mentioned c. Doping impurities d. Photo resist 11 / 50 The transistors used in BiCMOS are . . . . . . . . a. Both BJT and MOSFETs b. JFET c. BJT d. MOSFET 12 / 50 Substrate doping level should be decreased to avoid the latch-up effect. a. True b. False 13 / 50 Heavily doped polysilicon is deposited using . . . . . . a. Chemical vapour decomposition b. Chemical vapour deposition c. Chemical deposition d. Dry deposition 14 / 50 Surface mobility depends on . . . . . . . . a. Effective drain voltage b. Effective source voltage c. Effective gate voltage d. Channel length 15 / 50 BiCMOS inverter requires high load current sourcing a. False b. True 16 / 50 Ids depends on . . . . . . . a. Vss b. Vdd c. Vg d. Vds 17 / 50 What is the disadvantage of the MOS device? a. Unlimited current sinking b. Limited voltage sinking c. Limited current sourcing d. Limited voltage sourcing 18 / 50 Pass transistors are transistors used as . . . . . . . a. Inverters used in series b. Switches connected in series c. Switches connected in parallel d. Inverter used in parallel 19 / 50 Increasing fan-out . . . . . . . . the propagation delay. a. Does not affect b. Decreases c. Exponentially decreases d. Increases 20 / 50 The MOSFETS are arranged in this configuration to provide . . . . . . . . a. Both zero static power dissipation and high input impedance b. Zero static power dissipation c. High Input impedance d. None of the mentioned 21 / 50 For depletion mode transistor, gate should be connected to . . . . . . . . a. Ground b. Source c. Drain d. Positive voltage rail 22 / 50 What is the condition for non conducting mode? a. Vds lesser than Vgs b. Vgs = Vds = 0 c. Vgs = Vds = Vs = 0 d. Vgs lesser than Vds 23 / 50 CMOS technology is used in developing which of the following? a. Microprocessors b. All of the mentioned c. Microcontrollers d. Digital logic circuits 24 / 50 If the gate is given sufficiently large charge, electrons will be attracted to . . . . . . a. Channel region b. Drain region c. Switch region d. Bulk region 25 / 50 Fast gate can be built by keeping . . . . . . . . a. Low output capacitance b. Input capacitance does not affect speed of the gate c. High output capacitance d. High on resistance 26 / 50 In BiCMOS, MOS switches are used to . . . . . . a. To amplify the input voltage b. Drive output loads c. To perform logic functions d. Drive input loads 27 / 50 As die size shrinks, the complexity of making the photomasks . . . . . . . a. Increases b. Cannot be determined c. Remains the same d. Decreases 28 / 50 The current Ids . . . . . . . . as Vds increases. a. Remains fairly constant b. Decreases c. Increases d. Exponentially increases 29 / 50 The n-well collector is formed by . . . . . . . a. Lightly doped n-type epitaxial layer on p-Substrate b. Lightly doped n-type diffused layer on p-Substrate c. Heavily doped n-type diffused layer on p-Substrate d. Heavily doped n-type epitaxial layer on p-Substrate 30 / 50 Interconnection pattern is made on . . . . . . a. Polysilicon layer b. Silicon-di-oxide layer c. Metal layer d. Diffusion layer 31 / 50 If p-transistor is conducting and has small voltage between source and drain, then it is said to work in . .. . . a. Linear region b. Saturation region c. Non saturation resistive region d. Cut-off region 32 / 50 Transconductance gives the relationship between . . . . . . . a. Output current and output voltage b. Output current and input voltage c. Input current and input voltage d. Input current and output voltage 33 / 50 Latch-up is the generation of . . . . . . . a. Low impedance path b. High impedance path c. Low resistance path d. High resistance path 34 / 50 Increasing the transconductance . . . . . . a. Decreasing area occupied b. Increases input capacitance c. Decrease in output capacitance d. Decreasing input capacitance 35 / 50 The isolated active areas are created by technique known as . . . . . . a. None of the mentioned b. Etched field-oxide isolation or Local Oxidation of Silicon c. Local Oxidation of Silicon d. Etched field-oxide isolation 36 / 50 In latch-up condition, parasitic component gives rise to . . . . . . . . conducting path. a. Low resistance b. Low capacitance c. High resistance d. High capacitance 37 / 50 MOS transistor structure is . . . . . . a. Pseudo symmetrical b. Non symmetrical c. Semi symmetrical d. Symmetrical 38 / 50 Switching speed of a MOS device depends on . . . . . . a. Length channel b. Carrier mobility c. Gate voltage above a threshold d. All of the mentioned 39 / 50 Which of the following is true when inputs are controlled by equal amounts of charge? a. Cg(MOS) = Cbase(bipolar) b. Cg(MOS) greater than Cbase(bipolar) c. Cg(MOS) lesser than Cbase(bipolar) d. Cs(MOS) lesser than Cbase(bipolar) 40 / 50 N-well is formed by . . . . . . . . a. Decomposition b. Diffusion c. Filtering d. Dispersion 41 / 50 Positive photo resists are used more than negative photo resists because . . . . . . . . a. Negative photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the positive photo resists b. Negative photo resists are less sensitive to light c. Positive photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the negative photo resists d. Positive photo resists are less sensitive to light 42 / 50 Which process produces a circuit which is less prone to latch-up effect? a. BiCMOS b. CMOS c. nMOS d. pMOS 43 / 50 Increasing Vsb . . . . . . . . the threshold voltage. a. Decreases b. Does not effect c. Exponentially increases d. Increases 44 / 50 Depletion mode MOSFETs are more commonly used as . . . . . . . . a. Resistors b. Switches c. Capacitors d. Buffers 45 / 50 In nMOS fabrication, etching is done using . . . . . . . . . a. Plasma b. Sodium chloride c. Sulphuric acid d. Hydrochloric acid 46 / 50 What are the advantages of E-beam masks? a. Small feature size b. Looser layer c. Larger feature size d. Complex design 47 / 50 Which is used for the interconnection? a. Boron b. Aluminium c. Silicon d. Oxygen 48 / 50 The dopants are introduced in the active areas of silicon by using which process? a. Either Diffusion or Ion Implantation Process b. Ion Implantation process c. Diffusion process d. Chemical Vapour Deposition 49 / 50 Contact cuts are made in . . . . . . . . . a. Metal layer b. Diffusion layer c. Drain d. Source 50 / 50 Surface mobility depends on . . a. Effective gate voltage b. Effective source voltage c. Effective drain voltage d. Channel length Your score is LinkedIn Facebook VKontakte 0% Restart quiz Exit Anonymous feedback Thank you Send feedback Spread the love
