HomeElectronics Multiple choice question MCQ online testVLSI online test mcq (part1) VLSI online test mcq (part1) Leave a Comment / Electronics Multiple choice question MCQ online test Spread the love 0% Created on July 23, 2023VLSI VLSI (part1) 1 / 50 The BiCMOS are preferred over CMOS due to . . . . . . . . a. All of the mentioned b. Sensitivity is less with respect to the load capacitance c. High current drive capability d. Switching speed is more compared to CMOS 2 / 50 In nMOS inverter configuration depletion mode device is called as . . . . . . . a. None of the mentioned b. All of the mentioned c. Pull down d. Pull up 3 / 50 What are the advantages of BiCMOS? a. All of the mentioned b. Better noise characteristics c. High frequency characteristics d. Higher gain 4 / 50 Substrate bias voltage is positive for nMOS. a. True b. False 5 / 50 If both the transistors are in saturation, then they act as . . . . . . . . a. Divider b. Voltage source c. Buffer d. Current source 6 / 50 In CMOS inverter, transistor is a switch having . . . . . . . . a. Finite off resistance b. Buffer c. Infinite off resistance d. Infinite on resistance 7 / 50 Speed power product is measured as the product of . . . . . . . . a. Gate switching delay and gate power absorption b. Gate power dissipation and absorption c. Gate switching delay and gate power dissipation d. Gate switching delay and net gate power 8 / 50 In CMOS fabrication, the photoresist layer is exposed to . . . . . . . . a. Ultraviolet light b. Visible light c. Fluorescent d. Infra red light 9 / 50 Which has better I/A? a. nMOS b. pMOS c. CMOS d. Bipolar 10 / 50 The . . . . . . . . is used to reduce the resistivity of poly silicon. a. Doping impurities b. Photo resist c. Etching d. None of the mentioned 11 / 50 The transistors used in BiCMOS are . . . . . . . . a. JFET b. BJT c. MOSFET d. Both BJT and MOSFETs 12 / 50 Substrate doping level should be decreased to avoid the latch-up effect. a. True b. False 13 / 50 Heavily doped polysilicon is deposited using . . . . . . a. Chemical deposition b. Chemical vapour deposition c. Chemical vapour decomposition d. Dry deposition 14 / 50 Surface mobility depends on . . . . . . . . a. Channel length b. Effective source voltage c. Effective drain voltage d. Effective gate voltage 15 / 50 BiCMOS inverter requires high load current sourcing a. False b. True 16 / 50 Ids depends on . . . . . . . a. Vdd b. Vg c. Vss d. Vds 17 / 50 What is the disadvantage of the MOS device? a. Limited voltage sourcing b. Limited current sourcing c. Limited voltage sinking d. Unlimited current sinking 18 / 50 Pass transistors are transistors used as . . . . . . . a. Switches connected in series b. Switches connected in parallel c. Inverters used in series d. Inverter used in parallel 19 / 50 Increasing fan-out . . . . . . . . the propagation delay. a. Decreases b. Increases c. Does not affect d. Exponentially decreases 20 / 50 The MOSFETS are arranged in this configuration to provide . . . . . . . . a. Both zero static power dissipation and high input impedance b. None of the mentioned c. High Input impedance d. Zero static power dissipation 21 / 50 For depletion mode transistor, gate should be connected to . . . . . . . . a. Drain b. Source c. Ground d. Positive voltage rail 22 / 50 What is the condition for non conducting mode? a. Vgs = Vds = 0 b. Vgs = Vds = Vs = 0 c. Vgs lesser than Vds d. Vds lesser than Vgs 23 / 50 CMOS technology is used in developing which of the following? a. Digital logic circuits b. All of the mentioned c. Microprocessors d. Microcontrollers 24 / 50 If the gate is given sufficiently large charge, electrons will be attracted to . . . . . . a. Switch region b. Channel region c. Drain region d. Bulk region 25 / 50 Fast gate can be built by keeping . . . . . . . . a. High output capacitance b. Low output capacitance c. Input capacitance does not affect speed of the gate d. High on resistance 26 / 50 In BiCMOS, MOS switches are used to . . . . . . a. Drive output loads b. To perform logic functions c. To amplify the input voltage d. Drive input loads 27 / 50 As die size shrinks, the complexity of making the photomasks . . . . . . . a. Remains the same b. Decreases c. Cannot be determined d. Increases 28 / 50 The current Ids . . . . . . . . as Vds increases. a. Remains fairly constant b. Increases c. Decreases d. Exponentially increases 29 / 50 The n-well collector is formed by . . . . . . . a. Lightly doped n-type diffused layer on p-Substrate b. Lightly doped n-type epitaxial layer on p-Substrate c. Heavily doped n-type diffused layer on p-Substrate d. Heavily doped n-type epitaxial layer on p-Substrate 30 / 50 Interconnection pattern is made on . . . . . . a. Silicon-di-oxide layer b. Diffusion layer c. Metal layer d. Polysilicon layer 31 / 50 If p-transistor is conducting and has small voltage between source and drain, then it is said to work in . .. . . a. Linear region b. Saturation region c. Non saturation resistive region d. Cut-off region 32 / 50 Transconductance gives the relationship between . . . . . . . a. Output current and input voltage b. Input current and input voltage c. Input current and output voltage d. Output current and output voltage 33 / 50 Latch-up is the generation of . . . . . . . a. High resistance path b. High impedance path c. Low impedance path d. Low resistance path 34 / 50 Increasing the transconductance . . . . . . a. Decreasing area occupied b. Decrease in output capacitance c. Decreasing input capacitance d. Increases input capacitance 35 / 50 The isolated active areas are created by technique known as . . . . . . a. Local Oxidation of Silicon b. None of the mentioned c. Etched field-oxide isolation or Local Oxidation of Silicon d. Etched field-oxide isolation 36 / 50 In latch-up condition, parasitic component gives rise to . . . . . . . . conducting path. a. Low capacitance b. High capacitance c. High resistance d. Low resistance 37 / 50 MOS transistor structure is . . . . . . a. Non symmetrical b. Pseudo symmetrical c. Symmetrical d. Semi symmetrical 38 / 50 Switching speed of a MOS device depends on . . . . . . a. Gate voltage above a threshold b. Carrier mobility c. All of the mentioned d. Length channel 39 / 50 Which of the following is true when inputs are controlled by equal amounts of charge? a. Cs(MOS) lesser than Cbase(bipolar) b. Cg(MOS) lesser than Cbase(bipolar) c. Cg(MOS) greater than Cbase(bipolar) d. Cg(MOS) = Cbase(bipolar) 40 / 50 N-well is formed by . . . . . . . . a. Diffusion b. Decomposition c. Filtering d. Dispersion 41 / 50 Positive photo resists are used more than negative photo resists because . . . . . . . . a. Positive photo resists are less sensitive to light b. Negative photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the positive photo resists c. Positive photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the negative photo resists d. Negative photo resists are less sensitive to light 42 / 50 Which process produces a circuit which is less prone to latch-up effect? a. CMOS b. BiCMOS c. nMOS d. pMOS 43 / 50 Increasing Vsb . . . . . . . . the threshold voltage. a. Exponentially increases b. Decreases c. Increases d. Does not effect 44 / 50 Depletion mode MOSFETs are more commonly used as . . . . . . . . a. Switches b. Resistors c. Capacitors d. Buffers 45 / 50 In nMOS fabrication, etching is done using . . . . . . . . . a. Plasma b. Sodium chloride c. Hydrochloric acid d. Sulphuric acid 46 / 50 What are the advantages of E-beam masks? a. Small feature size b. Larger feature size c. Looser layer d. Complex design 47 / 50 Which is used for the interconnection? a. Silicon b. Boron c. Oxygen d. Aluminium 48 / 50 The dopants are introduced in the active areas of silicon by using which process? a. Either Diffusion or Ion Implantation Process b. Diffusion process c. Ion Implantation process d. Chemical Vapour Deposition 49 / 50 Contact cuts are made in . . . . . . . . . a. Metal layer b. Diffusion layer c. Drain d. Source 50 / 50 Surface mobility depends on . . a. Effective drain voltage b. Channel length c. Effective gate voltage d. Effective source voltage Your score is LinkedIn Facebook VKontakte 0% Restart quiz Exit Anonymous feedback Thank you Send feedback Spread the love
