HomeElectronics Multiple choice question MCQ online testVLSI online test mcq (part1) VLSI online test mcq (part1) Leave a Comment / Electronics Multiple choice question MCQ online test Spread the love 0% Created on July 23, 2023VLSI VLSI (part1) 1 / 50 The BiCMOS are preferred over CMOS due to . . . . . . . . a. All of the mentioned b. High current drive capability c. Switching speed is more compared to CMOS d. Sensitivity is less with respect to the load capacitance 2 / 50 In nMOS inverter configuration depletion mode device is called as . . . . . . . a. Pull down b. All of the mentioned c. None of the mentioned d. Pull up 3 / 50 What are the advantages of BiCMOS? a. All of the mentioned b. High frequency characteristics c. Higher gain d. Better noise characteristics 4 / 50 Substrate bias voltage is positive for nMOS. a. False b. True 5 / 50 If both the transistors are in saturation, then they act as . . . . . . . . a. Buffer b. Divider c. Current source d. Voltage source 6 / 50 In CMOS inverter, transistor is a switch having . . . . . . . . a. Finite off resistance b. Infinite off resistance c. Infinite on resistance d. Buffer 7 / 50 Speed power product is measured as the product of . . . . . . . . a. Gate switching delay and gate power absorption b. Gate power dissipation and absorption c. Gate switching delay and gate power dissipation d. Gate switching delay and net gate power 8 / 50 In CMOS fabrication, the photoresist layer is exposed to . . . . . . . . a. Infra red light b. Visible light c. Ultraviolet light d. Fluorescent 9 / 50 Which has better I/A? a. pMOS b. Bipolar c. nMOS d. CMOS 10 / 50 The . . . . . . . . is used to reduce the resistivity of poly silicon. a. None of the mentioned b. Photo resist c. Etching d. Doping impurities 11 / 50 The transistors used in BiCMOS are . . . . . . . . a. MOSFET b. BJT c. JFET d. Both BJT and MOSFETs 12 / 50 Substrate doping level should be decreased to avoid the latch-up effect. a. True b. False 13 / 50 Heavily doped polysilicon is deposited using . . . . . . a. Dry deposition b. Chemical deposition c. Chemical vapour deposition d. Chemical vapour decomposition 14 / 50 Surface mobility depends on . . . . . . . . a. Effective drain voltage b. Effective gate voltage c. Effective source voltage d. Channel length 15 / 50 BiCMOS inverter requires high load current sourcing a. False b. True 16 / 50 Ids depends on . . . . . . . a. Vdd b. Vds c. Vss d. Vg 17 / 50 What is the disadvantage of the MOS device? a. Limited voltage sourcing b. Limited current sourcing c. Unlimited current sinking d. Limited voltage sinking 18 / 50 Pass transistors are transistors used as . . . . . . . a. Switches connected in series b. Switches connected in parallel c. Inverters used in series d. Inverter used in parallel 19 / 50 Increasing fan-out . . . . . . . . the propagation delay. a. Increases b. Exponentially decreases c. Does not affect d. Decreases 20 / 50 The MOSFETS are arranged in this configuration to provide . . . . . . . . a. None of the mentioned b. Both zero static power dissipation and high input impedance c. High Input impedance d. Zero static power dissipation 21 / 50 For depletion mode transistor, gate should be connected to . . . . . . . . a. Source b. Positive voltage rail c. Ground d. Drain 22 / 50 What is the condition for non conducting mode? a. Vds lesser than Vgs b. Vgs = Vds = Vs = 0 c. Vgs = Vds = 0 d. Vgs lesser than Vds 23 / 50 CMOS technology is used in developing which of the following? a. Microcontrollers b. Digital logic circuits c. Microprocessors d. All of the mentioned 24 / 50 If the gate is given sufficiently large charge, electrons will be attracted to . . . . . . a. Channel region b. Switch region c. Drain region d. Bulk region 25 / 50 Fast gate can be built by keeping . . . . . . . . a. Low output capacitance b. Input capacitance does not affect speed of the gate c. High on resistance d. High output capacitance 26 / 50 In BiCMOS, MOS switches are used to . . . . . . a. To amplify the input voltage b. To perform logic functions c. Drive output loads d. Drive input loads 27 / 50 As die size shrinks, the complexity of making the photomasks . . . . . . . a. Decreases b. Cannot be determined c. Remains the same d. Increases 28 / 50 The current Ids . . . . . . . . as Vds increases. a. Exponentially increases b. Remains fairly constant c. Increases d. Decreases 29 / 50 The n-well collector is formed by . . . . . . . a. Lightly doped n-type epitaxial layer on p-Substrate b. Lightly doped n-type diffused layer on p-Substrate c. Heavily doped n-type diffused layer on p-Substrate d. Heavily doped n-type epitaxial layer on p-Substrate 30 / 50 Interconnection pattern is made on . . . . . . a. Diffusion layer b. Metal layer c. Polysilicon layer d. Silicon-di-oxide layer 31 / 50 If p-transistor is conducting and has small voltage between source and drain, then it is said to work in . .. . . a. Non saturation resistive region b. Linear region c. Saturation region d. Cut-off region 32 / 50 Transconductance gives the relationship between . . . . . . . a. Output current and output voltage b. Input current and output voltage c. Output current and input voltage d. Input current and input voltage 33 / 50 Latch-up is the generation of . . . . . . . a. Low resistance path b. High resistance path c. High impedance path d. Low impedance path 34 / 50 Increasing the transconductance . . . . . . a. Decreasing input capacitance b. Decreasing area occupied c. Decrease in output capacitance d. Increases input capacitance 35 / 50 The isolated active areas are created by technique known as . . . . . . a. Etched field-oxide isolation b. Etched field-oxide isolation or Local Oxidation of Silicon c. None of the mentioned d. Local Oxidation of Silicon 36 / 50 In latch-up condition, parasitic component gives rise to . . . . . . . . conducting path. a. High resistance b. Low resistance c. Low capacitance d. High capacitance 37 / 50 MOS transistor structure is . . . . . . a. Semi symmetrical b. Symmetrical c. Non symmetrical d. Pseudo symmetrical 38 / 50 Switching speed of a MOS device depends on . . . . . . a. Gate voltage above a threshold b. Carrier mobility c. All of the mentioned d. Length channel 39 / 50 Which of the following is true when inputs are controlled by equal amounts of charge? a. Cs(MOS) lesser than Cbase(bipolar) b. Cg(MOS) lesser than Cbase(bipolar) c. Cg(MOS) greater than Cbase(bipolar) d. Cg(MOS) = Cbase(bipolar) 40 / 50 N-well is formed by . . . . . . . . a. Filtering b. Diffusion c. Decomposition d. Dispersion 41 / 50 Positive photo resists are used more than negative photo resists because . . . . . . . . a. Positive photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the negative photo resists b. Negative photo resists are less sensitive to light c. Positive photo resists are less sensitive to light d. Negative photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the positive photo resists 42 / 50 Which process produces a circuit which is less prone to latch-up effect? a. pMOS b. BiCMOS c. nMOS d. CMOS 43 / 50 Increasing Vsb . . . . . . . . the threshold voltage. a. Exponentially increases b. Increases c. Does not effect d. Decreases 44 / 50 Depletion mode MOSFETs are more commonly used as . . . . . . . . a. Switches b. Resistors c. Buffers d. Capacitors 45 / 50 In nMOS fabrication, etching is done using . . . . . . . . . a. Plasma b. Hydrochloric acid c. Sulphuric acid d. Sodium chloride 46 / 50 What are the advantages of E-beam masks? a. Larger feature size b. Complex design c. Small feature size d. Looser layer 47 / 50 Which is used for the interconnection? a. Silicon b. Oxygen c. Aluminium d. Boron 48 / 50 The dopants are introduced in the active areas of silicon by using which process? a. Diffusion process b. Chemical Vapour Deposition c. Either Diffusion or Ion Implantation Process d. Ion Implantation process 49 / 50 Contact cuts are made in . . . . . . . . . a. Source b. Drain c. Metal layer d. Diffusion layer 50 / 50 Surface mobility depends on . . a. Channel length b. Effective gate voltage c. Effective source voltage d. Effective drain voltage Your score is LinkedIn Facebook VKontakte 0% Restart quiz Exit Anonymous feedback Thank you Send feedback Spread the love
