HomeElectronics Multiple choice question MCQ online testVLSI online test mcq (part1) VLSI online test mcq (part1) Leave a Comment / Electronics Multiple choice question MCQ online test Spread the love 0% Created on July 23, 2023VLSI VLSI (part1) 1 / 50 The BiCMOS are preferred over CMOS due to . . . . . . . . a. Sensitivity is less with respect to the load capacitance b. High current drive capability c. Switching speed is more compared to CMOS d. All of the mentioned 2 / 50 In nMOS inverter configuration depletion mode device is called as . . . . . . . a. Pull up b. Pull down c. None of the mentioned d. All of the mentioned 3 / 50 What are the advantages of BiCMOS? a. Higher gain b. Better noise characteristics c. High frequency characteristics d. All of the mentioned 4 / 50 Substrate bias voltage is positive for nMOS. a. False b. True 5 / 50 If both the transistors are in saturation, then they act as . . . . . . . . a. Divider b. Current source c. Buffer d. Voltage source 6 / 50 In CMOS inverter, transistor is a switch having . . . . . . . . a. Infinite on resistance b. Infinite off resistance c. Finite off resistance d. Buffer 7 / 50 Speed power product is measured as the product of . . . . . . . . a. Gate switching delay and gate power dissipation b. Gate switching delay and gate power absorption c. Gate power dissipation and absorption d. Gate switching delay and net gate power 8 / 50 In CMOS fabrication, the photoresist layer is exposed to . . . . . . . . a. Visible light b. Ultraviolet light c. Infra red light d. Fluorescent 9 / 50 Which has better I/A? a. pMOS b. CMOS c. nMOS d. Bipolar 10 / 50 The . . . . . . . . is used to reduce the resistivity of poly silicon. a. Doping impurities b. Photo resist c. Etching d. None of the mentioned 11 / 50 The transistors used in BiCMOS are . . . . . . . . a. BJT b. JFET c. Both BJT and MOSFETs d. MOSFET 12 / 50 Substrate doping level should be decreased to avoid the latch-up effect. a. True b. False 13 / 50 Heavily doped polysilicon is deposited using . . . . . . a. Chemical vapour deposition b. Dry deposition c. Chemical vapour decomposition d. Chemical deposition 14 / 50 Surface mobility depends on . . . . . . . . a. Effective gate voltage b. Effective drain voltage c. Channel length d. Effective source voltage 15 / 50 BiCMOS inverter requires high load current sourcing a. True b. False 16 / 50 Ids depends on . . . . . . . a. Vg b. Vss c. Vds d. Vdd 17 / 50 What is the disadvantage of the MOS device? a. Limited voltage sinking b. Unlimited current sinking c. Limited voltage sourcing d. Limited current sourcing 18 / 50 Pass transistors are transistors used as . . . . . . . a. Inverters used in series b. Switches connected in series c. Inverter used in parallel d. Switches connected in parallel 19 / 50 Increasing fan-out . . . . . . . . the propagation delay. a. Decreases b. Does not affect c. Exponentially decreases d. Increases 20 / 50 The MOSFETS are arranged in this configuration to provide . . . . . . . . a. None of the mentioned b. Zero static power dissipation c. High Input impedance d. Both zero static power dissipation and high input impedance 21 / 50 For depletion mode transistor, gate should be connected to . . . . . . . . a. Ground b. Drain c. Source d. Positive voltage rail 22 / 50 What is the condition for non conducting mode? a. Vgs = Vds = 0 b. Vgs lesser than Vds c. Vgs = Vds = Vs = 0 d. Vds lesser than Vgs 23 / 50 CMOS technology is used in developing which of the following? a. Digital logic circuits b. Microcontrollers c. All of the mentioned d. Microprocessors 24 / 50 If the gate is given sufficiently large charge, electrons will be attracted to . . . . . . a. Bulk region b. Switch region c. Channel region d. Drain region 25 / 50 Fast gate can be built by keeping . . . . . . . . a. Low output capacitance b. High on resistance c. High output capacitance d. Input capacitance does not affect speed of the gate 26 / 50 In BiCMOS, MOS switches are used to . . . . . . a. Drive input loads b. To amplify the input voltage c. To perform logic functions d. Drive output loads 27 / 50 As die size shrinks, the complexity of making the photomasks . . . . . . . a. Remains the same b. Decreases c. Increases d. Cannot be determined 28 / 50 The current Ids . . . . . . . . as Vds increases. a. Exponentially increases b. Remains fairly constant c. Increases d. Decreases 29 / 50 The n-well collector is formed by . . . . . . . a. Heavily doped n-type epitaxial layer on p-Substrate b. Lightly doped n-type epitaxial layer on p-Substrate c. Lightly doped n-type diffused layer on p-Substrate d. Heavily doped n-type diffused layer on p-Substrate 30 / 50 Interconnection pattern is made on . . . . . . a. Polysilicon layer b. Diffusion layer c. Silicon-di-oxide layer d. Metal layer 31 / 50 If p-transistor is conducting and has small voltage between source and drain, then it is said to work in . .. . . a. Non saturation resistive region b. Saturation region c. Cut-off region d. Linear region 32 / 50 Transconductance gives the relationship between . . . . . . . a. Output current and output voltage b. Output current and input voltage c. Input current and output voltage d. Input current and input voltage 33 / 50 Latch-up is the generation of . . . . . . . a. High impedance path b. High resistance path c. Low impedance path d. Low resistance path 34 / 50 Increasing the transconductance . . . . . . a. Decreasing area occupied b. Decrease in output capacitance c. Increases input capacitance d. Decreasing input capacitance 35 / 50 The isolated active areas are created by technique known as . . . . . . a. Local Oxidation of Silicon b. Etched field-oxide isolation or Local Oxidation of Silicon c. Etched field-oxide isolation d. None of the mentioned 36 / 50 In latch-up condition, parasitic component gives rise to . . . . . . . . conducting path. a. Low capacitance b. Low resistance c. High capacitance d. High resistance 37 / 50 MOS transistor structure is . . . . . . a. Symmetrical b. Semi symmetrical c. Non symmetrical d. Pseudo symmetrical 38 / 50 Switching speed of a MOS device depends on . . . . . . a. All of the mentioned b. Length channel c. Gate voltage above a threshold d. Carrier mobility 39 / 50 Which of the following is true when inputs are controlled by equal amounts of charge? a. Cs(MOS) lesser than Cbase(bipolar) b. Cg(MOS) greater than Cbase(bipolar) c. Cg(MOS) = Cbase(bipolar) d. Cg(MOS) lesser than Cbase(bipolar) 40 / 50 N-well is formed by . . . . . . . . a. Dispersion b. Filtering c. Decomposition d. Diffusion 41 / 50 Positive photo resists are used more than negative photo resists because . . . . . . . . a. Negative photo resists are less sensitive to light b. Positive photo resists are less sensitive to light c. Negative photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the positive photo resists d. Positive photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the negative photo resists 42 / 50 Which process produces a circuit which is less prone to latch-up effect? a. BiCMOS b. nMOS c. CMOS d. pMOS 43 / 50 Increasing Vsb . . . . . . . . the threshold voltage. a. Increases b. Does not effect c. Decreases d. Exponentially increases 44 / 50 Depletion mode MOSFETs are more commonly used as . . . . . . . . a. Capacitors b. Resistors c. Switches d. Buffers 45 / 50 In nMOS fabrication, etching is done using . . . . . . . . . a. Sulphuric acid b. Plasma c. Hydrochloric acid d. Sodium chloride 46 / 50 What are the advantages of E-beam masks? a. Larger feature size b. Complex design c. Small feature size d. Looser layer 47 / 50 Which is used for the interconnection? a. Aluminium b. Silicon c. Oxygen d. Boron 48 / 50 The dopants are introduced in the active areas of silicon by using which process? a. Chemical Vapour Deposition b. Ion Implantation process c. Either Diffusion or Ion Implantation Process d. Diffusion process 49 / 50 Contact cuts are made in . . . . . . . . . a. Metal layer b. Source c. Diffusion layer d. Drain 50 / 50 Surface mobility depends on . . a. Channel length b. Effective gate voltage c. Effective drain voltage d. Effective source voltage Your score is LinkedIn Facebook VKontakte 0% Restart quiz Exit Anonymous feedback Thank you Send feedback Spread the love
