HomeElectronics Multiple choice question MCQ online testVLSI online test mcq (part1) VLSI online test mcq (part1) Leave a Comment / Electronics Multiple choice question MCQ online test Spread the love 0% Created on July 23, 2023VLSI VLSI (part1) 1 / 50 The BiCMOS are preferred over CMOS due to . . . . . . . . a. High current drive capability b. Sensitivity is less with respect to the load capacitance c. Switching speed is more compared to CMOS d. All of the mentioned 2 / 50 In nMOS inverter configuration depletion mode device is called as . . . . . . . a. All of the mentioned b. Pull down c. None of the mentioned d. Pull up 3 / 50 What are the advantages of BiCMOS? a. Better noise characteristics b. Higher gain c. High frequency characteristics d. All of the mentioned 4 / 50 Substrate bias voltage is positive for nMOS. a. False b. True 5 / 50 If both the transistors are in saturation, then they act as . . . . . . . . a. Divider b. Current source c. Buffer d. Voltage source 6 / 50 In CMOS inverter, transistor is a switch having . . . . . . . . a. Finite off resistance b. Infinite off resistance c. Buffer d. Infinite on resistance 7 / 50 Speed power product is measured as the product of . . . . . . . . a. Gate power dissipation and absorption b. Gate switching delay and net gate power c. Gate switching delay and gate power absorption d. Gate switching delay and gate power dissipation 8 / 50 In CMOS fabrication, the photoresist layer is exposed to . . . . . . . . a. Visible light b. Infra red light c. Ultraviolet light d. Fluorescent 9 / 50 Which has better I/A? a. Bipolar b. nMOS c. CMOS d. pMOS 10 / 50 The . . . . . . . . is used to reduce the resistivity of poly silicon. a. Doping impurities b. Photo resist c. None of the mentioned d. Etching 11 / 50 The transistors used in BiCMOS are . . . . . . . . a. Both BJT and MOSFETs b. JFET c. BJT d. MOSFET 12 / 50 Substrate doping level should be decreased to avoid the latch-up effect. a. False b. True 13 / 50 Heavily doped polysilicon is deposited using . . . . . . a. Dry deposition b. Chemical vapour decomposition c. Chemical deposition d. Chemical vapour deposition 14 / 50 Surface mobility depends on . . . . . . . . a. Channel length b. Effective gate voltage c. Effective drain voltage d. Effective source voltage 15 / 50 BiCMOS inverter requires high load current sourcing a. False b. True 16 / 50 Ids depends on . . . . . . . a. Vds b. Vdd c. Vg d. Vss 17 / 50 What is the disadvantage of the MOS device? a. Unlimited current sinking b. Limited voltage sourcing c. Limited voltage sinking d. Limited current sourcing 18 / 50 Pass transistors are transistors used as . . . . . . . a. Inverter used in parallel b. Inverters used in series c. Switches connected in series d. Switches connected in parallel 19 / 50 Increasing fan-out . . . . . . . . the propagation delay. a. Decreases b. Increases c. Exponentially decreases d. Does not affect 20 / 50 The MOSFETS are arranged in this configuration to provide . . . . . . . . a. Zero static power dissipation b. None of the mentioned c. Both zero static power dissipation and high input impedance d. High Input impedance 21 / 50 For depletion mode transistor, gate should be connected to . . . . . . . . a. Source b. Ground c. Positive voltage rail d. Drain 22 / 50 What is the condition for non conducting mode? a. Vgs = Vds = 0 b. Vgs lesser than Vds c. Vgs = Vds = Vs = 0 d. Vds lesser than Vgs 23 / 50 CMOS technology is used in developing which of the following? a. All of the mentioned b. Microprocessors c. Microcontrollers d. Digital logic circuits 24 / 50 If the gate is given sufficiently large charge, electrons will be attracted to . . . . . . a. Switch region b. Drain region c. Bulk region d. Channel region 25 / 50 Fast gate can be built by keeping . . . . . . . . a. High on resistance b. Input capacitance does not affect speed of the gate c. Low output capacitance d. High output capacitance 26 / 50 In BiCMOS, MOS switches are used to . . . . . . a. Drive output loads b. Drive input loads c. To amplify the input voltage d. To perform logic functions 27 / 50 As die size shrinks, the complexity of making the photomasks . . . . . . . a. Cannot be determined b. Remains the same c. Decreases d. Increases 28 / 50 The current Ids . . . . . . . . as Vds increases. a. Exponentially increases b. Decreases c. Increases d. Remains fairly constant 29 / 50 The n-well collector is formed by . . . . . . . a. Lightly doped n-type epitaxial layer on p-Substrate b. Lightly doped n-type diffused layer on p-Substrate c. Heavily doped n-type epitaxial layer on p-Substrate d. Heavily doped n-type diffused layer on p-Substrate 30 / 50 Interconnection pattern is made on . . . . . . a. Diffusion layer b. Metal layer c. Silicon-di-oxide layer d. Polysilicon layer 31 / 50 If p-transistor is conducting and has small voltage between source and drain, then it is said to work in . .. . . a. Non saturation resistive region b. Cut-off region c. Linear region d. Saturation region 32 / 50 Transconductance gives the relationship between . . . . . . . a. Input current and input voltage b. Input current and output voltage c. Output current and output voltage d. Output current and input voltage 33 / 50 Latch-up is the generation of . . . . . . . a. High impedance path b. High resistance path c. Low resistance path d. Low impedance path 34 / 50 Increasing the transconductance . . . . . . a. Increases input capacitance b. Decrease in output capacitance c. Decreasing input capacitance d. Decreasing area occupied 35 / 50 The isolated active areas are created by technique known as . . . . . . a. Etched field-oxide isolation or Local Oxidation of Silicon b. None of the mentioned c. Local Oxidation of Silicon d. Etched field-oxide isolation 36 / 50 In latch-up condition, parasitic component gives rise to . . . . . . . . conducting path. a. High capacitance b. High resistance c. Low capacitance d. Low resistance 37 / 50 MOS transistor structure is . . . . . . a. Pseudo symmetrical b. Non symmetrical c. Semi symmetrical d. Symmetrical 38 / 50 Switching speed of a MOS device depends on . . . . . . a. Length channel b. Gate voltage above a threshold c. Carrier mobility d. All of the mentioned 39 / 50 Which of the following is true when inputs are controlled by equal amounts of charge? a. Cs(MOS) lesser than Cbase(bipolar) b. Cg(MOS) = Cbase(bipolar) c. Cg(MOS) lesser than Cbase(bipolar) d. Cg(MOS) greater than Cbase(bipolar) 40 / 50 N-well is formed by . . . . . . . . a. Diffusion b. Dispersion c. Filtering d. Decomposition 41 / 50 Positive photo resists are used more than negative photo resists because . . . . . . . . a. Negative photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the positive photo resists b. Positive photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the negative photo resists c. Positive photo resists are less sensitive to light d. Negative photo resists are less sensitive to light 42 / 50 Which process produces a circuit which is less prone to latch-up effect? a. pMOS b. nMOS c. BiCMOS d. CMOS 43 / 50 Increasing Vsb . . . . . . . . the threshold voltage. a. Increases b. Does not effect c. Decreases d. Exponentially increases 44 / 50 Depletion mode MOSFETs are more commonly used as . . . . . . . . a. Resistors b. Buffers c. Switches d. Capacitors 45 / 50 In nMOS fabrication, etching is done using . . . . . . . . . a. Plasma b. Hydrochloric acid c. Sodium chloride d. Sulphuric acid 46 / 50 What are the advantages of E-beam masks? a. Larger feature size b. Looser layer c. Complex design d. Small feature size 47 / 50 Which is used for the interconnection? a. Boron b. Aluminium c. Oxygen d. Silicon 48 / 50 The dopants are introduced in the active areas of silicon by using which process? a. Diffusion process b. Ion Implantation process c. Either Diffusion or Ion Implantation Process d. Chemical Vapour Deposition 49 / 50 Contact cuts are made in . . . . . . . . . a. Drain b. Diffusion layer c. Source d. Metal layer 50 / 50 Surface mobility depends on . . a. Effective drain voltage b. Channel length c. Effective gate voltage d. Effective source voltage Your score is LinkedIn Facebook VKontakte 0% Restart quiz Exit Anonymous feedback Thank you Send feedback Spread the love
