HomeElectronics Multiple choice question MCQ online testVLSI online test mcq (part1) VLSI online test mcq (part1) Leave a Comment / Electronics Multiple choice question MCQ online test Spread the love 0% Created on July 23, 2023VLSI VLSI (part1) 1 / 50 The BiCMOS are preferred over CMOS due to . . . . . . . . a. All of the mentioned b. Sensitivity is less with respect to the load capacitance c. High current drive capability d. Switching speed is more compared to CMOS 2 / 50 In nMOS inverter configuration depletion mode device is called as . . . . . . . a. All of the mentioned b. Pull up c. None of the mentioned d. Pull down 3 / 50 What are the advantages of BiCMOS? a. Higher gain b. High frequency characteristics c. Better noise characteristics d. All of the mentioned 4 / 50 Substrate bias voltage is positive for nMOS. a. True b. False 5 / 50 If both the transistors are in saturation, then they act as . . . . . . . . a. Divider b. Buffer c. Current source d. Voltage source 6 / 50 In CMOS inverter, transistor is a switch having . . . . . . . . a. Buffer b. Infinite off resistance c. Infinite on resistance d. Finite off resistance 7 / 50 Speed power product is measured as the product of . . . . . . . . a. Gate switching delay and net gate power b. Gate switching delay and gate power dissipation c. Gate power dissipation and absorption d. Gate switching delay and gate power absorption 8 / 50 In CMOS fabrication, the photoresist layer is exposed to . . . . . . . . a. Visible light b. Fluorescent c. Ultraviolet light d. Infra red light 9 / 50 Which has better I/A? a. pMOS b. CMOS c. Bipolar d. nMOS 10 / 50 The . . . . . . . . is used to reduce the resistivity of poly silicon. a. Etching b. Photo resist c. Doping impurities d. None of the mentioned 11 / 50 The transistors used in BiCMOS are . . . . . . . . a. JFET b. BJT c. Both BJT and MOSFETs d. MOSFET 12 / 50 Substrate doping level should be decreased to avoid the latch-up effect. a. False b. True 13 / 50 Heavily doped polysilicon is deposited using . . . . . . a. Chemical deposition b. Chemical vapour deposition c. Chemical vapour decomposition d. Dry deposition 14 / 50 Surface mobility depends on . . . . . . . . a. Effective gate voltage b. Channel length c. Effective source voltage d. Effective drain voltage 15 / 50 BiCMOS inverter requires high load current sourcing a. True b. False 16 / 50 Ids depends on . . . . . . . a. Vg b. Vdd c. Vss d. Vds 17 / 50 What is the disadvantage of the MOS device? a. Limited current sourcing b. Limited voltage sinking c. Unlimited current sinking d. Limited voltage sourcing 18 / 50 Pass transistors are transistors used as . . . . . . . a. Inverter used in parallel b. Inverters used in series c. Switches connected in series d. Switches connected in parallel 19 / 50 Increasing fan-out . . . . . . . . the propagation delay. a. Decreases b. Increases c. Exponentially decreases d. Does not affect 20 / 50 The MOSFETS are arranged in this configuration to provide . . . . . . . . a. Both zero static power dissipation and high input impedance b. High Input impedance c. Zero static power dissipation d. None of the mentioned 21 / 50 For depletion mode transistor, gate should be connected to . . . . . . . . a. Positive voltage rail b. Ground c. Drain d. Source 22 / 50 What is the condition for non conducting mode? a. Vgs lesser than Vds b. Vds lesser than Vgs c. Vgs = Vds = Vs = 0 d. Vgs = Vds = 0 23 / 50 CMOS technology is used in developing which of the following? a. All of the mentioned b. Digital logic circuits c. Microprocessors d. Microcontrollers 24 / 50 If the gate is given sufficiently large charge, electrons will be attracted to . . . . . . a. Bulk region b. Drain region c. Channel region d. Switch region 25 / 50 Fast gate can be built by keeping . . . . . . . . a. Low output capacitance b. High output capacitance c. Input capacitance does not affect speed of the gate d. High on resistance 26 / 50 In BiCMOS, MOS switches are used to . . . . . . a. Drive input loads b. Drive output loads c. To amplify the input voltage d. To perform logic functions 27 / 50 As die size shrinks, the complexity of making the photomasks . . . . . . . a. Decreases b. Remains the same c. Increases d. Cannot be determined 28 / 50 The current Ids . . . . . . . . as Vds increases. a. Exponentially increases b. Remains fairly constant c. Increases d. Decreases 29 / 50 The n-well collector is formed by . . . . . . . a. Lightly doped n-type diffused layer on p-Substrate b. Heavily doped n-type diffused layer on p-Substrate c. Lightly doped n-type epitaxial layer on p-Substrate d. Heavily doped n-type epitaxial layer on p-Substrate 30 / 50 Interconnection pattern is made on . . . . . . a. Silicon-di-oxide layer b. Polysilicon layer c. Metal layer d. Diffusion layer 31 / 50 If p-transistor is conducting and has small voltage between source and drain, then it is said to work in . .. . . a. Linear region b. Saturation region c. Cut-off region d. Non saturation resistive region 32 / 50 Transconductance gives the relationship between . . . . . . . a. Output current and input voltage b. Output current and output voltage c. Input current and output voltage d. Input current and input voltage 33 / 50 Latch-up is the generation of . . . . . . . a. Low impedance path b. High impedance path c. Low resistance path d. High resistance path 34 / 50 Increasing the transconductance . . . . . . a. Decreasing area occupied b. Increases input capacitance c. Decreasing input capacitance d. Decrease in output capacitance 35 / 50 The isolated active areas are created by technique known as . . . . . . a. Etched field-oxide isolation or Local Oxidation of Silicon b. Etched field-oxide isolation c. None of the mentioned d. Local Oxidation of Silicon 36 / 50 In latch-up condition, parasitic component gives rise to . . . . . . . . conducting path. a. Low capacitance b. Low resistance c. High capacitance d. High resistance 37 / 50 MOS transistor structure is . . . . . . a. Symmetrical b. Non symmetrical c. Semi symmetrical d. Pseudo symmetrical 38 / 50 Switching speed of a MOS device depends on . . . . . . a. Carrier mobility b. Gate voltage above a threshold c. All of the mentioned d. Length channel 39 / 50 Which of the following is true when inputs are controlled by equal amounts of charge? a. Cs(MOS) lesser than Cbase(bipolar) b. Cg(MOS) lesser than Cbase(bipolar) c. Cg(MOS) greater than Cbase(bipolar) d. Cg(MOS) = Cbase(bipolar) 40 / 50 N-well is formed by . . . . . . . . a. Diffusion b. Filtering c. Dispersion d. Decomposition 41 / 50 Positive photo resists are used more than negative photo resists because . . . . . . . . a. Negative photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the positive photo resists b. Positive photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the negative photo resists c. Positive photo resists are less sensitive to light d. Negative photo resists are less sensitive to light 42 / 50 Which process produces a circuit which is less prone to latch-up effect? a. pMOS b. BiCMOS c. nMOS d. CMOS 43 / 50 Increasing Vsb . . . . . . . . the threshold voltage. a. Decreases b. Increases c. Exponentially increases d. Does not effect 44 / 50 Depletion mode MOSFETs are more commonly used as . . . . . . . . a. Buffers b. Switches c. Resistors d. Capacitors 45 / 50 In nMOS fabrication, etching is done using . . . . . . . . . a. Hydrochloric acid b. Sodium chloride c. Plasma d. Sulphuric acid 46 / 50 What are the advantages of E-beam masks? a. Larger feature size b. Small feature size c. Looser layer d. Complex design 47 / 50 Which is used for the interconnection? a. Silicon b. Aluminium c. Boron d. Oxygen 48 / 50 The dopants are introduced in the active areas of silicon by using which process? a. Diffusion process b. Chemical Vapour Deposition c. Ion Implantation process d. Either Diffusion or Ion Implantation Process 49 / 50 Contact cuts are made in . . . . . . . . . a. Drain b. Source c. Metal layer d. Diffusion layer 50 / 50 Surface mobility depends on . . a. Effective gate voltage b. Channel length c. Effective drain voltage d. Effective source voltage Your score is LinkedIn Facebook VKontakte 0% Restart quiz Exit Anonymous feedback Thank you Send feedback Spread the love
