HomeElectronics Multiple choice question MCQ online testVLSI online test mcq (part1) VLSI online test mcq (part1) Leave a Comment / Electronics Multiple choice question MCQ online test Spread the love 0% Created on July 23, 2023VLSI VLSI (part1) 1 / 50 The BiCMOS are preferred over CMOS due to . . . . . . . . a. High current drive capability b. Sensitivity is less with respect to the load capacitance c. Switching speed is more compared to CMOS d. All of the mentioned 2 / 50 In nMOS inverter configuration depletion mode device is called as . . . . . . . a. Pull down b. Pull up c. All of the mentioned d. None of the mentioned 3 / 50 What are the advantages of BiCMOS? a. High frequency characteristics b. Higher gain c. All of the mentioned d. Better noise characteristics 4 / 50 Substrate bias voltage is positive for nMOS. a. True b. False 5 / 50 If both the transistors are in saturation, then they act as . . . . . . . . a. Divider b. Buffer c. Current source d. Voltage source 6 / 50 In CMOS inverter, transistor is a switch having . . . . . . . . a. Infinite off resistance b. Buffer c. Finite off resistance d. Infinite on resistance 7 / 50 Speed power product is measured as the product of . . . . . . . . a. Gate switching delay and gate power dissipation b. Gate switching delay and net gate power c. Gate power dissipation and absorption d. Gate switching delay and gate power absorption 8 / 50 In CMOS fabrication, the photoresist layer is exposed to . . . . . . . . a. Infra red light b. Visible light c. Ultraviolet light d. Fluorescent 9 / 50 Which has better I/A? a. pMOS b. CMOS c. Bipolar d. nMOS 10 / 50 The . . . . . . . . is used to reduce the resistivity of poly silicon. a. Doping impurities b. Photo resist c. None of the mentioned d. Etching 11 / 50 The transistors used in BiCMOS are . . . . . . . . a. MOSFET b. BJT c. Both BJT and MOSFETs d. JFET 12 / 50 Substrate doping level should be decreased to avoid the latch-up effect. a. False b. True 13 / 50 Heavily doped polysilicon is deposited using . . . . . . a. Chemical vapour deposition b. Dry deposition c. Chemical deposition d. Chemical vapour decomposition 14 / 50 Surface mobility depends on . . . . . . . . a. Effective source voltage b. Effective gate voltage c. Effective drain voltage d. Channel length 15 / 50 BiCMOS inverter requires high load current sourcing a. False b. True 16 / 50 Ids depends on . . . . . . . a. Vg b. Vdd c. Vds d. Vss 17 / 50 What is the disadvantage of the MOS device? a. Unlimited current sinking b. Limited voltage sourcing c. Limited current sourcing d. Limited voltage sinking 18 / 50 Pass transistors are transistors used as . . . . . . . a. Inverters used in series b. Inverter used in parallel c. Switches connected in series d. Switches connected in parallel 19 / 50 Increasing fan-out . . . . . . . . the propagation delay. a. Exponentially decreases b. Increases c. Decreases d. Does not affect 20 / 50 The MOSFETS are arranged in this configuration to provide . . . . . . . . a. Both zero static power dissipation and high input impedance b. None of the mentioned c. Zero static power dissipation d. High Input impedance 21 / 50 For depletion mode transistor, gate should be connected to . . . . . . . . a. Positive voltage rail b. Drain c. Source d. Ground 22 / 50 What is the condition for non conducting mode? a. Vgs = Vds = Vs = 0 b. Vgs lesser than Vds c. Vds lesser than Vgs d. Vgs = Vds = 0 23 / 50 CMOS technology is used in developing which of the following? a. Microcontrollers b. All of the mentioned c. Digital logic circuits d. Microprocessors 24 / 50 If the gate is given sufficiently large charge, electrons will be attracted to . . . . . . a. Switch region b. Drain region c. Channel region d. Bulk region 25 / 50 Fast gate can be built by keeping . . . . . . . . a. High on resistance b. Input capacitance does not affect speed of the gate c. Low output capacitance d. High output capacitance 26 / 50 In BiCMOS, MOS switches are used to . . . . . . a. To perform logic functions b. Drive output loads c. To amplify the input voltage d. Drive input loads 27 / 50 As die size shrinks, the complexity of making the photomasks . . . . . . . a. Decreases b. Remains the same c. Cannot be determined d. Increases 28 / 50 The current Ids . . . . . . . . as Vds increases. a. Exponentially increases b. Decreases c. Increases d. Remains fairly constant 29 / 50 The n-well collector is formed by . . . . . . . a. Heavily doped n-type diffused layer on p-Substrate b. Lightly doped n-type epitaxial layer on p-Substrate c. Heavily doped n-type epitaxial layer on p-Substrate d. Lightly doped n-type diffused layer on p-Substrate 30 / 50 Interconnection pattern is made on . . . . . . a. Silicon-di-oxide layer b. Polysilicon layer c. Metal layer d. Diffusion layer 31 / 50 If p-transistor is conducting and has small voltage between source and drain, then it is said to work in . .. . . a. Linear region b. Saturation region c. Cut-off region d. Non saturation resistive region 32 / 50 Transconductance gives the relationship between . . . . . . . a. Output current and output voltage b. Input current and input voltage c. Input current and output voltage d. Output current and input voltage 33 / 50 Latch-up is the generation of . . . . . . . a. High impedance path b. Low resistance path c. Low impedance path d. High resistance path 34 / 50 Increasing the transconductance . . . . . . a. Decrease in output capacitance b. Decreasing area occupied c. Increases input capacitance d. Decreasing input capacitance 35 / 50 The isolated active areas are created by technique known as . . . . . . a. Local Oxidation of Silicon b. Etched field-oxide isolation c. None of the mentioned d. Etched field-oxide isolation or Local Oxidation of Silicon 36 / 50 In latch-up condition, parasitic component gives rise to . . . . . . . . conducting path. a. Low resistance b. High capacitance c. Low capacitance d. High resistance 37 / 50 MOS transistor structure is . . . . . . a. Symmetrical b. Pseudo symmetrical c. Non symmetrical d. Semi symmetrical 38 / 50 Switching speed of a MOS device depends on . . . . . . a. Gate voltage above a threshold b. Length channel c. Carrier mobility d. All of the mentioned 39 / 50 Which of the following is true when inputs are controlled by equal amounts of charge? a. Cg(MOS) greater than Cbase(bipolar) b. Cs(MOS) lesser than Cbase(bipolar) c. Cg(MOS) lesser than Cbase(bipolar) d. Cg(MOS) = Cbase(bipolar) 40 / 50 N-well is formed by . . . . . . . . a. Diffusion b. Decomposition c. Filtering d. Dispersion 41 / 50 Positive photo resists are used more than negative photo resists because . . . . . . . . a. Negative photo resists are less sensitive to light b. Positive photo resists are less sensitive to light c. Positive photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the negative photo resists d. Negative photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the positive photo resists 42 / 50 Which process produces a circuit which is less prone to latch-up effect? a. nMOS b. pMOS c. BiCMOS d. CMOS 43 / 50 Increasing Vsb . . . . . . . . the threshold voltage. a. Exponentially increases b. Decreases c. Does not effect d. Increases 44 / 50 Depletion mode MOSFETs are more commonly used as . . . . . . . . a. Resistors b. Switches c. Capacitors d. Buffers 45 / 50 In nMOS fabrication, etching is done using . . . . . . . . . a. Hydrochloric acid b. Plasma c. Sulphuric acid d. Sodium chloride 46 / 50 What are the advantages of E-beam masks? a. Larger feature size b. Small feature size c. Complex design d. Looser layer 47 / 50 Which is used for the interconnection? a. Aluminium b. Boron c. Oxygen d. Silicon 48 / 50 The dopants are introduced in the active areas of silicon by using which process? a. Chemical Vapour Deposition b. Either Diffusion or Ion Implantation Process c. Ion Implantation process d. Diffusion process 49 / 50 Contact cuts are made in . . . . . . . . . a. Diffusion layer b. Source c. Metal layer d. Drain 50 / 50 Surface mobility depends on . . a. Effective source voltage b. Effective gate voltage c. Channel length d. Effective drain voltage Your score is LinkedIn Facebook VKontakte 0% Restart quiz Exit Anonymous feedback Thank you Send feedback Spread the love
