HomeElectronics Multiple choice question MCQ online testVLSI online test mcq (part1) VLSI online test mcq (part1) Leave a Comment / Electronics Multiple choice question MCQ online test Spread the love 0% Created on July 23, 2023VLSI VLSI (part1) 1 / 50 The BiCMOS are preferred over CMOS due to . . . . . . . . a. All of the mentioned b. Sensitivity is less with respect to the load capacitance c. High current drive capability d. Switching speed is more compared to CMOS 2 / 50 In nMOS inverter configuration depletion mode device is called as . . . . . . . a. All of the mentioned b. Pull down c. Pull up d. None of the mentioned 3 / 50 What are the advantages of BiCMOS? a. High frequency characteristics b. Higher gain c. All of the mentioned d. Better noise characteristics 4 / 50 Substrate bias voltage is positive for nMOS. a. False b. True 5 / 50 If both the transistors are in saturation, then they act as . . . . . . . . a. Divider b. Voltage source c. Buffer d. Current source 6 / 50 In CMOS inverter, transistor is a switch having . . . . . . . . a. Finite off resistance b. Infinite on resistance c. Infinite off resistance d. Buffer 7 / 50 Speed power product is measured as the product of . . . . . . . . a. Gate switching delay and gate power absorption b. Gate power dissipation and absorption c. Gate switching delay and gate power dissipation d. Gate switching delay and net gate power 8 / 50 In CMOS fabrication, the photoresist layer is exposed to . . . . . . . . a. Infra red light b. Visible light c. Ultraviolet light d. Fluorescent 9 / 50 Which has better I/A? a. Bipolar b. CMOS c. nMOS d. pMOS 10 / 50 The . . . . . . . . is used to reduce the resistivity of poly silicon. a. Photo resist b. None of the mentioned c. Doping impurities d. Etching 11 / 50 The transistors used in BiCMOS are . . . . . . . . a. Both BJT and MOSFETs b. JFET c. BJT d. MOSFET 12 / 50 Substrate doping level should be decreased to avoid the latch-up effect. a. True b. False 13 / 50 Heavily doped polysilicon is deposited using . . . . . . a. Chemical vapour decomposition b. Chemical deposition c. Dry deposition d. Chemical vapour deposition 14 / 50 Surface mobility depends on . . . . . . . . a. Effective drain voltage b. Effective gate voltage c. Effective source voltage d. Channel length 15 / 50 BiCMOS inverter requires high load current sourcing a. True b. False 16 / 50 Ids depends on . . . . . . . a. Vg b. Vss c. Vdd d. Vds 17 / 50 What is the disadvantage of the MOS device? a. Limited voltage sinking b. Limited current sourcing c. Limited voltage sourcing d. Unlimited current sinking 18 / 50 Pass transistors are transistors used as . . . . . . . a. Inverter used in parallel b. Switches connected in parallel c. Inverters used in series d. Switches connected in series 19 / 50 Increasing fan-out . . . . . . . . the propagation delay. a. Decreases b. Increases c. Does not affect d. Exponentially decreases 20 / 50 The MOSFETS are arranged in this configuration to provide . . . . . . . . a. High Input impedance b. Both zero static power dissipation and high input impedance c. Zero static power dissipation d. None of the mentioned 21 / 50 For depletion mode transistor, gate should be connected to . . . . . . . . a. Ground b. Positive voltage rail c. Source d. Drain 22 / 50 What is the condition for non conducting mode? a. Vgs = Vds = Vs = 0 b. Vgs = Vds = 0 c. Vds lesser than Vgs d. Vgs lesser than Vds 23 / 50 CMOS technology is used in developing which of the following? a. Microprocessors b. All of the mentioned c. Microcontrollers d. Digital logic circuits 24 / 50 If the gate is given sufficiently large charge, electrons will be attracted to . . . . . . a. Channel region b. Drain region c. Switch region d. Bulk region 25 / 50 Fast gate can be built by keeping . . . . . . . . a. High output capacitance b. High on resistance c. Low output capacitance d. Input capacitance does not affect speed of the gate 26 / 50 In BiCMOS, MOS switches are used to . . . . . . a. To amplify the input voltage b. Drive output loads c. To perform logic functions d. Drive input loads 27 / 50 As die size shrinks, the complexity of making the photomasks . . . . . . . a. Cannot be determined b. Decreases c. Increases d. Remains the same 28 / 50 The current Ids . . . . . . . . as Vds increases. a. Decreases b. Exponentially increases c. Remains fairly constant d. Increases 29 / 50 The n-well collector is formed by . . . . . . . a. Heavily doped n-type epitaxial layer on p-Substrate b. Heavily doped n-type diffused layer on p-Substrate c. Lightly doped n-type diffused layer on p-Substrate d. Lightly doped n-type epitaxial layer on p-Substrate 30 / 50 Interconnection pattern is made on . . . . . . a. Diffusion layer b. Polysilicon layer c. Metal layer d. Silicon-di-oxide layer 31 / 50 If p-transistor is conducting and has small voltage between source and drain, then it is said to work in . .. . . a. Cut-off region b. Saturation region c. Linear region d. Non saturation resistive region 32 / 50 Transconductance gives the relationship between . . . . . . . a. Input current and input voltage b. Output current and input voltage c. Output current and output voltage d. Input current and output voltage 33 / 50 Latch-up is the generation of . . . . . . . a. Low impedance path b. High resistance path c. Low resistance path d. High impedance path 34 / 50 Increasing the transconductance . . . . . . a. Decreasing area occupied b. Increases input capacitance c. Decrease in output capacitance d. Decreasing input capacitance 35 / 50 The isolated active areas are created by technique known as . . . . . . a. Local Oxidation of Silicon b. Etched field-oxide isolation c. None of the mentioned d. Etched field-oxide isolation or Local Oxidation of Silicon 36 / 50 In latch-up condition, parasitic component gives rise to . . . . . . . . conducting path. a. Low capacitance b. High capacitance c. Low resistance d. High resistance 37 / 50 MOS transistor structure is . . . . . . a. Non symmetrical b. Pseudo symmetrical c. Symmetrical d. Semi symmetrical 38 / 50 Switching speed of a MOS device depends on . . . . . . a. All of the mentioned b. Length channel c. Gate voltage above a threshold d. Carrier mobility 39 / 50 Which of the following is true when inputs are controlled by equal amounts of charge? a. Cg(MOS) lesser than Cbase(bipolar) b. Cg(MOS) = Cbase(bipolar) c. Cg(MOS) greater than Cbase(bipolar) d. Cs(MOS) lesser than Cbase(bipolar) 40 / 50 N-well is formed by . . . . . . . . a. Decomposition b. Dispersion c. Diffusion d. Filtering 41 / 50 Positive photo resists are used more than negative photo resists because . . . . . . . . a. Positive photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the negative photo resists b. Negative photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the positive photo resists c. Positive photo resists are less sensitive to light d. Negative photo resists are less sensitive to light 42 / 50 Which process produces a circuit which is less prone to latch-up effect? a. CMOS b. pMOS c. nMOS d. BiCMOS 43 / 50 Increasing Vsb . . . . . . . . the threshold voltage. a. Decreases b. Increases c. Does not effect d. Exponentially increases 44 / 50 Depletion mode MOSFETs are more commonly used as . . . . . . . . a. Buffers b. Switches c. Resistors d. Capacitors 45 / 50 In nMOS fabrication, etching is done using . . . . . . . . . a. Hydrochloric acid b. Sulphuric acid c. Plasma d. Sodium chloride 46 / 50 What are the advantages of E-beam masks? a. Complex design b. Small feature size c. Larger feature size d. Looser layer 47 / 50 Which is used for the interconnection? a. Silicon b. Oxygen c. Aluminium d. Boron 48 / 50 The dopants are introduced in the active areas of silicon by using which process? a. Either Diffusion or Ion Implantation Process b. Chemical Vapour Deposition c. Diffusion process d. Ion Implantation process 49 / 50 Contact cuts are made in . . . . . . . . . a. Source b. Diffusion layer c. Metal layer d. Drain 50 / 50 Surface mobility depends on . . a. Effective gate voltage b. Channel length c. Effective drain voltage d. Effective source voltage Your score is LinkedIn Facebook VKontakte 0% Restart quiz Exit Anonymous feedback Thank you Send feedback Spread the love
