HomeElectronics Multiple choice question MCQ online testVLSI online test mcq (part1) VLSI online test mcq (part1) Leave a Comment / Electronics Multiple choice question MCQ online test Spread the love 0% Created on July 23, 2023VLSI VLSI (part1) 1 / 50 The BiCMOS are preferred over CMOS due to . . . . . . . . a. Sensitivity is less with respect to the load capacitance b. Switching speed is more compared to CMOS c. High current drive capability d. All of the mentioned 2 / 50 In nMOS inverter configuration depletion mode device is called as . . . . . . . a. Pull up b. All of the mentioned c. Pull down d. None of the mentioned 3 / 50 What are the advantages of BiCMOS? a. Better noise characteristics b. All of the mentioned c. High frequency characteristics d. Higher gain 4 / 50 Substrate bias voltage is positive for nMOS. a. True b. False 5 / 50 If both the transistors are in saturation, then they act as . . . . . . . . a. Divider b. Current source c. Voltage source d. Buffer 6 / 50 In CMOS inverter, transistor is a switch having . . . . . . . . a. Finite off resistance b. Infinite off resistance c. Buffer d. Infinite on resistance 7 / 50 Speed power product is measured as the product of . . . . . . . . a. Gate switching delay and gate power absorption b. Gate switching delay and net gate power c. Gate switching delay and gate power dissipation d. Gate power dissipation and absorption 8 / 50 In CMOS fabrication, the photoresist layer is exposed to . . . . . . . . a. Fluorescent b. Infra red light c. Ultraviolet light d. Visible light 9 / 50 Which has better I/A? a. CMOS b. pMOS c. nMOS d. Bipolar 10 / 50 The . . . . . . . . is used to reduce the resistivity of poly silicon. a. Photo resist b. Etching c. None of the mentioned d. Doping impurities 11 / 50 The transistors used in BiCMOS are . . . . . . . . a. JFET b. Both BJT and MOSFETs c. MOSFET d. BJT 12 / 50 Substrate doping level should be decreased to avoid the latch-up effect. a. True b. False 13 / 50 Heavily doped polysilicon is deposited using . . . . . . a. Chemical vapour deposition b. Dry deposition c. Chemical deposition d. Chemical vapour decomposition 14 / 50 Surface mobility depends on . . . . . . . . a. Effective source voltage b. Channel length c. Effective drain voltage d. Effective gate voltage 15 / 50 BiCMOS inverter requires high load current sourcing a. True b. False 16 / 50 Ids depends on . . . . . . . a. Vss b. Vdd c. Vds d. Vg 17 / 50 What is the disadvantage of the MOS device? a. Limited current sourcing b. Unlimited current sinking c. Limited voltage sourcing d. Limited voltage sinking 18 / 50 Pass transistors are transistors used as . . . . . . . a. Switches connected in series b. Inverters used in series c. Inverter used in parallel d. Switches connected in parallel 19 / 50 Increasing fan-out . . . . . . . . the propagation delay. a. Does not affect b. Decreases c. Exponentially decreases d. Increases 20 / 50 The MOSFETS are arranged in this configuration to provide . . . . . . . . a. Zero static power dissipation b. Both zero static power dissipation and high input impedance c. None of the mentioned d. High Input impedance 21 / 50 For depletion mode transistor, gate should be connected to . . . . . . . . a. Ground b. Drain c. Positive voltage rail d. Source 22 / 50 What is the condition for non conducting mode? a. Vgs = Vds = 0 b. Vgs lesser than Vds c. Vds lesser than Vgs d. Vgs = Vds = Vs = 0 23 / 50 CMOS technology is used in developing which of the following? a. All of the mentioned b. Microcontrollers c. Digital logic circuits d. Microprocessors 24 / 50 If the gate is given sufficiently large charge, electrons will be attracted to . . . . . . a. Drain region b. Switch region c. Bulk region d. Channel region 25 / 50 Fast gate can be built by keeping . . . . . . . . a. Low output capacitance b. High on resistance c. High output capacitance d. Input capacitance does not affect speed of the gate 26 / 50 In BiCMOS, MOS switches are used to . . . . . . a. Drive input loads b. To amplify the input voltage c. To perform logic functions d. Drive output loads 27 / 50 As die size shrinks, the complexity of making the photomasks . . . . . . . a. Decreases b. Cannot be determined c. Increases d. Remains the same 28 / 50 The current Ids . . . . . . . . as Vds increases. a. Decreases b. Exponentially increases c. Increases d. Remains fairly constant 29 / 50 The n-well collector is formed by . . . . . . . a. Heavily doped n-type epitaxial layer on p-Substrate b. Lightly doped n-type epitaxial layer on p-Substrate c. Lightly doped n-type diffused layer on p-Substrate d. Heavily doped n-type diffused layer on p-Substrate 30 / 50 Interconnection pattern is made on . . . . . . a. Polysilicon layer b. Metal layer c. Diffusion layer d. Silicon-di-oxide layer 31 / 50 If p-transistor is conducting and has small voltage between source and drain, then it is said to work in . .. . . a. Cut-off region b. Saturation region c. Non saturation resistive region d. Linear region 32 / 50 Transconductance gives the relationship between . . . . . . . a. Output current and input voltage b. Input current and input voltage c. Output current and output voltage d. Input current and output voltage 33 / 50 Latch-up is the generation of . . . . . . . a. High resistance path b. Low impedance path c. High impedance path d. Low resistance path 34 / 50 Increasing the transconductance . . . . . . a. Increases input capacitance b. Decrease in output capacitance c. Decreasing input capacitance d. Decreasing area occupied 35 / 50 The isolated active areas are created by technique known as . . . . . . a. Local Oxidation of Silicon b. None of the mentioned c. Etched field-oxide isolation or Local Oxidation of Silicon d. Etched field-oxide isolation 36 / 50 In latch-up condition, parasitic component gives rise to . . . . . . . . conducting path. a. High capacitance b. Low resistance c. High resistance d. Low capacitance 37 / 50 MOS transistor structure is . . . . . . a. Non symmetrical b. Pseudo symmetrical c. Semi symmetrical d. Symmetrical 38 / 50 Switching speed of a MOS device depends on . . . . . . a. Length channel b. Gate voltage above a threshold c. Carrier mobility d. All of the mentioned 39 / 50 Which of the following is true when inputs are controlled by equal amounts of charge? a. Cs(MOS) lesser than Cbase(bipolar) b. Cg(MOS) = Cbase(bipolar) c. Cg(MOS) greater than Cbase(bipolar) d. Cg(MOS) lesser than Cbase(bipolar) 40 / 50 N-well is formed by . . . . . . . . a. Filtering b. Decomposition c. Dispersion d. Diffusion 41 / 50 Positive photo resists are used more than negative photo resists because . . . . . . . . a. Positive photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the negative photo resists b. Positive photo resists are less sensitive to light c. Negative photo resists are less sensitive to light d. Negative photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the positive photo resists 42 / 50 Which process produces a circuit which is less prone to latch-up effect? a. BiCMOS b. CMOS c. nMOS d. pMOS 43 / 50 Increasing Vsb . . . . . . . . the threshold voltage. a. Decreases b. Increases c. Exponentially increases d. Does not effect 44 / 50 Depletion mode MOSFETs are more commonly used as . . . . . . . . a. Resistors b. Capacitors c. Buffers d. Switches 45 / 50 In nMOS fabrication, etching is done using . . . . . . . . . a. Hydrochloric acid b. Sodium chloride c. Sulphuric acid d. Plasma 46 / 50 What are the advantages of E-beam masks? a. Larger feature size b. Complex design c. Looser layer d. Small feature size 47 / 50 Which is used for the interconnection? a. Silicon b. Aluminium c. Boron d. Oxygen 48 / 50 The dopants are introduced in the active areas of silicon by using which process? a. Chemical Vapour Deposition b. Diffusion process c. Either Diffusion or Ion Implantation Process d. Ion Implantation process 49 / 50 Contact cuts are made in . . . . . . . . . a. Diffusion layer b. Drain c. Source d. Metal layer 50 / 50 Surface mobility depends on . . a. Effective source voltage b. Channel length c. Effective drain voltage d. Effective gate voltage Your score is LinkedIn Facebook VKontakte 0% Restart quiz Exit Anonymous feedback Thank you Send feedback Spread the love
