Combinational Logic Design MCQ {part2}

Share this

0%
0 votes, 0 avg
4
Created on

Digital electronics

Combinational Logic Design {part 2}

tail spin

1 / 24

Category: Combinational Logic Design

1. A parallel adder in which the carry-out of each full-adder is the carry-in to the next significant digit adder is called a

2 / 24

Category: Combinational Logic Design

2. In digital systems subtraction is performed

3 / 24

Category: Combinational Logic Design

3. Which of the following logic circuits accepts two binary digits on inputs, and produces two binary digits, a sum bit and a carry bit on its outputs?

4 / 24

Category: Combinational Logic Design

4. In a digital system BCD arithmetic is preferred to normal binary arithmetic because

5 / 24

Category: Combinational Logic Design

5. The adder preferred for applications where circuit minimization is more important than speed
is

6 / 24

Category: Combinational Logic Design

6. How many inputs and outputs does a full-adder have?

7 / 24

Category: Combinational Logic Design

7. A logic circuit that responds to just one input, in accordance with some priority system, among those that may be simultaneously high is called

8 / 24

Category: Combinational Logic Design

8. How many inputs and outputs does a full-subtractor circuit have?

9 / 24

Category: Combinational Logic Design

9. To secure a higher speed of addition, which of the following is the preferred solution?

10 / 24

Category: Combinational Logic Design

10. In BCD addition, 0110 is required to be added to the sum for getting the correct result, if

11 / 24

Category: Combinational Logic Design

11. The minimum number of 2-input NAND/NOR gates required to realize a half-adder is

12 / 24

Category: Combinational Logic Design

12. In which of the following adder circuits is the carry ripple delay eliminated?

13 / 24

Category: Combinational Logic Design

13. A full-adder can be realized using

14 / 24

Category: Combinational Logic Design

14. The logic gate used in parity checkers is

15 / 24

Category: Combinational Logic Design

15. Which logic gate is a basic comparator?

16 / 24

Category: Combinational Logic Design

16. How many full-adders are required to construct an m-bit parallel adder?

17 / 24

Category: Combinational Logic Design

17. BCD subtraction is performed by using

18 / 24

Category: Combinational Logic Design

18. Parallel adders are

19 / 24

Category: Combinational Logic Design

19. The minimum number of 2-input NOR gates required to realize a full-subtractor is

20 / 24

Category: Combinational Logic Design

20. The minimum number of 2-input NAND/NOR gates required to realize a half-subtractor is

21 / 24

Category: Combinational Logic Design

21. The minimum number of 2-input NAND gates required to realize a full adder/full-subtractor is

22 / 24

Category: Combinational Logic Design

22. A serial adder requires only one

23 / 24

Category: Combinational Logic Design

23. The difference output in a full-subtractor is the same as the

24 / 24

Category: Combinational Logic Design

24. A device whose inputs are decimal digits and/or alphabetic characters and whose outputs are the coded representations of those inputs is called

Your score is

The average score is 2%

0%

Exit

Thank you

Share this

Leave a Comment

Your email address will not be published. Required fields are marked *