Combinational Logic Design MCQ {part2} Leave a Comment / Electronics Multiple choice question MCQ Share this 0% 0 votes, 0 avg 1 Created on November 29, 2022 By AdminDigital electronics Combinational Logic Design {part 2} 1 / 24 Category: Combinational Logic Design 1. A full-adder can be realized using two half-adders, one AND gate two half-adders, two OR gates two half-adders, one OR gate one half-adder, two OR gates 2 / 24 Category: Combinational Logic Design 2. In BCD addition, 0110 is required to be added to the sum for getting the correct result, if none of these the sum of two BCD numbers is not a valid BCD number the suni of two BCD numbers is not a valid BCD number or a carry is produced a carry is produced 3 / 24 Category: Combinational Logic Design 3. How many inputs and outputs does a full-subtractor circuit have? three inputs, two outputs two inputs, three outputs two inputs, one output two inputs, two outputs 4 / 24 Category: Combinational Logic Design 4. How many full-adders are required to construct an m-bit parallel adder? m-1 m+ 1 m/2 m 5 / 24 Category: Combinational Logic Design 5. How many inputs and outputs does a full-adder have? two inputs, three outputs three inputs, two outputs two inputs, two outputs two inputs, one output 6 / 24 Category: Combinational Logic Design 6. BCD subtraction is performed by using 9â€™s complement representation 1â€™s complement representation 2â€™s complement representation Sâ€™s complement representation 7 / 24 Category: Combinational Logic Design 7. In which of the following adder circuits is the carry ripple delay eliminated? half-adder parallel adder full-adder carry-look-ahead adder 8 / 24 Category: Combinational Logic Design 8. In a digital system BCD arithmetic is preferred to normal binary arithmetic because BCD arithmetic circuits are simpler than binary arithmetic circuits BCD arithmetic circuits are less expensive than binary arithmetic circuits BCD arithmetic circuits are faster than binary arithmetic circuits of ease of operation when input is in BCD format and the output display is decimal 9 / 24 Category: Combinational Logic Design 9. To secure a higher speed of addition, which of the following is the preferred solution? full-adder serial adder adder with a look-ahead-carry parallel adder 10 / 24 Category: Combinational Logic Design 10. Parallel adders are Both none of these sequential logic circuits combinational logic circuits 11 / 24 Category: Combinational Logic Design 11. A serial adder requires only one multiplexer half-adder full-adde counter 12 / 24 Category: Combinational Logic Design 12. A device whose inputs are decimal digits and/or alphabetic characters and whose outputs are the coded representations of those inputs is called an encoder a decimal converter a code converter a decode 13 / 24 Category: Combinational Logic Design 13. The difference output in a full-subtractor is the same as the difference output of a half-subtractor sum output of a full-adder sum output of a half-adder carry output of a full-adder 14 / 24 Category: Combinational Logic Design 14. A parallel adder in which the carry-out of each full-adder is the carry-in to the next significant digit adder is called a serial carry adder look-ahead-carry adder parallel carry adder ripple carry adder 15 / 24 Category: Combinational Logic Design 15. The minimum number of 2-input NOR gates required to realize a full-subtractor is 10 12 8 9 16 / 24 Category: Combinational Logic Design 16. The adder preferred for applications where circuit minimization is more important than speedis half-adder full-adder parallel adder serial adder 17 / 24 Category: Combinational Logic Design 17. Which logic gate is a basic comparator? NAND gate X-NOR gate NOR gate X-OR gate 18 / 24 Category: Combinational Logic Design 18. Which of the following logic circuits accepts two binary digits on inputs, and produces two binary digits, a sum bit and a carry bit on its outputs? serial adder half-adder full-adder parallel adder 19 / 24 Category: Combinational Logic Design 19. In digital systems subtraction is performed using half-adders using half-subtractors using adders with 1â€™s complement representation of negative numbers by none of these 20 / 24 Category: Combinational Logic Design 20. The logic gate used in parity checkers is NAND gate X-OR gate NOR gate X-NOR gate 21 / 24 Category: Combinational Logic Design 21. The minimum number of 2-input NAND/NOR gates required to realize a half-subtractor is 3 5 6 4 22 / 24 Category: Combinational Logic Design 22. A logic circuit that responds to just one input, in accordance with some priority system, among those that may be simultaneously high is called a priority encoder an encode a priority decoder a decoder 23 / 24 Category: Combinational Logic Design 23. The minimum number of 2-input NAND gates required to realize a full adder/full-subtractor is 6 5 3 4 24 / 24 Category: Combinational Logic Design 24. The minimum number of 2-input NAND/NOR gates required to realize a half-adder is 6 4 5 3 Your score is The average score is 4% LinkedIn Facebook Twitter VKontakte 0% Restart quiz Exit Send feedback Share this