Combinational Logic Design MCQ {part2} Leave a Comment / Electronics Multiple choice question MCQ online test Share this 0% 0 votes, 0 avg 2 Created on June 12, 2023Digital electronics Combinational Logic Design {part 2} 1 / 24 Category: Combinational Logic Design 1. Parallel adders are a) sequential logic circuits b) combinational logic circuits c) Both d) none of these 2 / 24 Category: Combinational Logic Design 2. How many inputs and outputs does a full-adder have? a) two inputs, three outputs b) two inputs, two outputs c) three inputs, two outputs d) two inputs, one output 3 / 24 Category: Combinational Logic Design 3. A full-adder can be realized using a) two half-adders, one AND gate b) two half-adders, two OR gates c) one half-adder, two OR gates d) two half-adders, one OR gate 4 / 24 Category: Combinational Logic Design 4. A serial adder requires only one a) multiplexer b) full-adde c) counter d) half-adder 5 / 24 Category: Combinational Logic Design 5. The adder preferred for applications where circuit minimization is more important than speedis a) half-adder b) serial adder c) full-adder d) parallel adder 6 / 24 Category: Combinational Logic Design 6. The logic gate used in parity checkers is a) X-OR gate b) X-NOR gate c) NOR gate d) NAND gate 7 / 24 Category: Combinational Logic Design 7. The minimum number of 2-input NAND/NOR gates required to realize a half-adder is a) 6 b) 3 c) 4 d) 5 8 / 24 Category: Combinational Logic Design 8. Which logic gate is a basic comparator? a) NOR gate b) X-NOR gate c) X-OR gate d) NAND gate 9 / 24 Category: Combinational Logic Design 9. The minimum number of 2-input NAND gates required to realize a full adder/full-subtractor is a) 3 b) 5 c) 4 d) 6 10 / 24 Category: Combinational Logic Design 10. To secure a higher speed of addition, which of the following is the preferred solution? a) serial adder b) full-adder c) parallel adder d) adder with a look-ahead-carry 11 / 24 Category: Combinational Logic Design 11. A device whose inputs are decimal digits and/or alphabetic characters and whose outputs are the coded representations of those inputs is called a) a code converter b) a decode c) an encoder d) a decimal converter 12 / 24 Category: Combinational Logic Design 12. In BCD addition, 0110 is required to be added to the sum for getting the correct result, if a) none of these b) the sum of two BCD numbers is not a valid BCD number c) a carry is produced d) the suni of two BCD numbers is not a valid BCD number or a carry is produced 13 / 24 Category: Combinational Logic Design 13. A parallel adder in which the carry-out of each full-adder is the carry-in to the next significant digit adder is called a a) ripple carry adder b) serial carry adder c) look-ahead-carry adder d) parallel carry adder 14 / 24 Category: Combinational Logic Design 14. The difference output in a full-subtractor is the same as the a) difference output of a half-subtractor b) carry output of a full-adder c) sum output of a half-adder d) sum output of a full-adder 15 / 24 Category: Combinational Logic Design 15. In a digital system BCD arithmetic is preferred to normal binary arithmetic because a) BCD arithmetic circuits are simpler than binary arithmetic circuits b) of ease of operation when input is in BCD format and the output display is decimal c) BCD arithmetic circuits are less expensive than binary arithmetic circuits d) BCD arithmetic circuits are faster than binary arithmetic circuits 16 / 24 Category: Combinational Logic Design 16. BCD subtraction is performed by using a) S’s complement representation b) 9’s complement representation c) 2’s complement representation d) 1’s complement representation 17 / 24 Category: Combinational Logic Design 17. In digital systems subtraction is performed a) using half-subtractors b) by none of these c) using adders with 1’s complement representation of negative numbers d) using half-adders 18 / 24 Category: Combinational Logic Design 18. The minimum number of 2-input NOR gates required to realize a full-subtractor is a) 10 b) 12 c) 9 d) 8 19 / 24 Category: Combinational Logic Design 19. How many full-adders are required to construct an m-bit parallel adder? a) m b) m-1 c) m/2 d) m+ 1 20 / 24 Category: Combinational Logic Design 20. In which of the following adder circuits is the carry ripple delay eliminated? a) half-adder b) parallel adder c) carry-look-ahead adder d) full-adder 21 / 24 Category: Combinational Logic Design 21. How many inputs and outputs does a full-subtractor circuit have? a) two inputs, two outputs b) two inputs, one output c) three inputs, two outputs d) two inputs, three outputs 22 / 24 Category: Combinational Logic Design 22. A logic circuit that responds to just one input, in accordance with some priority system, among those that may be simultaneously high is called a) a priority encoder b) a decoder c) a priority decoder d) an encode 23 / 24 Category: Combinational Logic Design 23. The minimum number of 2-input NAND/NOR gates required to realize a half-subtractor is a) 3 b) 4 c) 5 d) 6 24 / 24 Category: Combinational Logic Design 24. Which of the following logic circuits accepts two binary digits on inputs, and produces two binary digits, a sum bit and a carry bit on its outputs? a) half-adder b) serial adder c) full-adder d) parallel adder Your score is The average score is 4% LinkedIn Facebook Twitter VKontakte 0% Restart quiz Exit Thank you Send feedback Share this