Combinational Logic Design MCQ {part2}

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Combinational Logic Design {part 2}

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Category: Combinational Logic Design

1. In a digital system BCD arithmetic is preferred to normal binary arithmetic because

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Category: Combinational Logic Design

2. How many full-adders are required to construct an m-bit parallel adder?

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Category: Combinational Logic Design

3. A parallel adder in which the carry-out of each full-adder is the carry-in to the next significant digit adder is called a

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Category: Combinational Logic Design

4. A full-adder can be realized using

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Category: Combinational Logic Design

5. The minimum number of 2-input NAND/NOR gates required to realize a half-adder is

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Category: Combinational Logic Design

6. Which of the following logic circuits accepts two binary digits on inputs, and produces two binary digits, a sum bit and a carry bit on its outputs?

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Category: Combinational Logic Design

7. In BCD addition, 0110 is required to be added to the sum for getting the correct result, if

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Category: Combinational Logic Design

8. A serial adder requires only one

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Category: Combinational Logic Design

9. How many inputs and outputs does a full-subtractor circuit have?

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Category: Combinational Logic Design

10. The difference output in a full-subtractor is the same as the

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Category: Combinational Logic Design

11. BCD subtraction is performed by using

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Category: Combinational Logic Design

12. In which of the following adder circuits is the carry ripple delay eliminated?

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Category: Combinational Logic Design

13. A logic circuit that responds to just one input, in accordance with some priority system, among those that may be simultaneously high is called

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Category: Combinational Logic Design

14. The minimum number of 2-input NAND/NOR gates required to realize a half-subtractor is

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Category: Combinational Logic Design

15. The adder preferred for applications where circuit minimization is more important than speed
is

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Category: Combinational Logic Design

16. Which logic gate is a basic comparator?

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Category: Combinational Logic Design

17. A device whose inputs are decimal digits and/or alphabetic characters and whose outputs are the coded representations of those inputs is called

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Category: Combinational Logic Design

18. How many inputs and outputs does a full-adder have?

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Category: Combinational Logic Design

19. The minimum number of 2-input NOR gates required to realize a full-subtractor is

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Category: Combinational Logic Design

20. The logic gate used in parity checkers is

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Category: Combinational Logic Design

21. The minimum number of 2-input NAND gates required to realize a full adder/full-subtractor is

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Category: Combinational Logic Design

22. To secure a higher speed of addition, which of the following is the preferred solution?

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Category: Combinational Logic Design

23. Parallel adders are

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Category: Combinational Logic Design

24. In digital systems subtraction is performed

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