HomeElectronics Multiple choice question MCQ online testCombinational Logic Design MCQ {part2} Combinational Logic Design MCQ {part2} Leave a Comment / Electronics Multiple choice question MCQ online test Share this 0% 0 votes, 0 avg 4 Created on June 12, 2023Digital electronics Combinational Logic Design {part 2} 1 / 24 Category: Combinational Logic Design 1. A parallel adder in which the carry-out of each full-adder is the carry-in to the next significant digit adder is called a a) ripple carry adder b) look-ahead-carry adder c) parallel carry adder d) serial carry adder 2 / 24 Category: Combinational Logic Design 2. In digital systems subtraction is performed a) using half-adders b) using half-subtractors c) using adders with 1’s complement representation of negative numbers d) by none of these 3 / 24 Category: Combinational Logic Design 3. Which of the following logic circuits accepts two binary digits on inputs, and produces two binary digits, a sum bit and a carry bit on its outputs? a) serial adder b) parallel adder c) half-adder d) full-adder 4 / 24 Category: Combinational Logic Design 4. In a digital system BCD arithmetic is preferred to normal binary arithmetic because a) of ease of operation when input is in BCD format and the output display is decimal b) BCD arithmetic circuits are less expensive than binary arithmetic circuits c) BCD arithmetic circuits are simpler than binary arithmetic circuits d) BCD arithmetic circuits are faster than binary arithmetic circuits 5 / 24 Category: Combinational Logic Design 5. The adder preferred for applications where circuit minimization is more important than speedis a) parallel adder b) half-adder c) serial adder d) full-adder 6 / 24 Category: Combinational Logic Design 6. How many inputs and outputs does a full-adder have? a) three inputs, two outputs b) two inputs, three outputs c) two inputs, one output d) two inputs, two outputs 7 / 24 Category: Combinational Logic Design 7. A logic circuit that responds to just one input, in accordance with some priority system, among those that may be simultaneously high is called a) an encode b) a decoder c) a priority decoder d) a priority encoder 8 / 24 Category: Combinational Logic Design 8. How many inputs and outputs does a full-subtractor circuit have? a) two inputs, three outputs b) two inputs, two outputs c) three inputs, two outputs d) two inputs, one output 9 / 24 Category: Combinational Logic Design 9. To secure a higher speed of addition, which of the following is the preferred solution? a) full-adder b) adder with a look-ahead-carry c) parallel adder d) serial adder 10 / 24 Category: Combinational Logic Design 10. In BCD addition, 0110 is required to be added to the sum for getting the correct result, if a) none of these b) the suni of two BCD numbers is not a valid BCD number or a carry is produced c) a carry is produced d) the sum of two BCD numbers is not a valid BCD number 11 / 24 Category: Combinational Logic Design 11. The minimum number of 2-input NAND/NOR gates required to realize a half-adder is a) 4 b) 3 c) 6 d) 5 12 / 24 Category: Combinational Logic Design 12. In which of the following adder circuits is the carry ripple delay eliminated? a) parallel adder b) carry-look-ahead adder c) half-adder d) full-adder 13 / 24 Category: Combinational Logic Design 13. A full-adder can be realized using a) one half-adder, two OR gates b) two half-adders, one OR gate c) two half-adders, one AND gate d) two half-adders, two OR gates 14 / 24 Category: Combinational Logic Design 14. The logic gate used in parity checkers is a) NOR gate b) X-OR gate c) NAND gate d) X-NOR gate 15 / 24 Category: Combinational Logic Design 15. Which logic gate is a basic comparator? a) X-NOR gate b) NOR gate c) X-OR gate d) NAND gate 16 / 24 Category: Combinational Logic Design 16. How many full-adders are required to construct an m-bit parallel adder? a) m-1 b) m+ 1 c) m/2 d) m 17 / 24 Category: Combinational Logic Design 17. BCD subtraction is performed by using a) 2’s complement representation b) 9’s complement representation c) S’s complement representation d) 1’s complement representation 18 / 24 Category: Combinational Logic Design 18. Parallel adders are a) sequential logic circuits b) none of these c) combinational logic circuits d) Both 19 / 24 Category: Combinational Logic Design 19. The minimum number of 2-input NOR gates required to realize a full-subtractor is a) 9 b) 10 c) 8 d) 12 20 / 24 Category: Combinational Logic Design 20. The minimum number of 2-input NAND/NOR gates required to realize a half-subtractor is a) 3 b) 4 c) 5 d) 6 21 / 24 Category: Combinational Logic Design 21. The minimum number of 2-input NAND gates required to realize a full adder/full-subtractor is a) 4 b) 3 c) 6 d) 5 22 / 24 Category: Combinational Logic Design 22. A serial adder requires only one a) half-adder b) multiplexer c) counter d) full-adde 23 / 24 Category: Combinational Logic Design 23. The difference output in a full-subtractor is the same as the a) difference output of a half-subtractor b) carry output of a full-adder c) sum output of a half-adder d) sum output of a full-adder 24 / 24 Category: Combinational Logic Design 24. A device whose inputs are decimal digits and/or alphabetic characters and whose outputs are the coded representations of those inputs is called a) a decode b) a decimal converter c) a code converter d) an encoder Your score isThe average score is 2% LinkedIn Facebook Twitter VKontakte 0% Restart quiz Exit Thank you Send feedback Share this