Combinational Logic Design MCQ {part2} Leave a Comment / Electronics Multiple choice question MCQ Share this 0% 0 votes, 0 avg 1 Created on November 29, 2022 By AdminDigital electronics Combinational Logic Design {part 2} 1 / 24 Category: Combinational Logic Design 1. A device whose inputs are decimal digits and/or alphabetic characters and whose outputs are the coded representations of those inputs is called a decode a code converter a decimal converter an encoder 2 / 24 Category: Combinational Logic Design 2. BCD subtraction is performed by using 9’s complement representation 1’s complement representation S’s complement representation 2’s complement representation 3 / 24 Category: Combinational Logic Design 3. A serial adder requires only one multiplexer full-adde half-adder counter 4 / 24 Category: Combinational Logic Design 4. In digital systems subtraction is performed using half-adders using adders with 1’s complement representation of negative numbers by none of these using half-subtractors 5 / 24 Category: Combinational Logic Design 5. The minimum number of 2-input NAND/NOR gates required to realize a half-subtractor is 4 6 3 5 6 / 24 Category: Combinational Logic Design 6. A parallel adder in which the carry-out of each full-adder is the carry-in to the next significant digit adder is called a look-ahead-carry adder serial carry adder parallel carry adder ripple carry adder 7 / 24 Category: Combinational Logic Design 7. Which of the following logic circuits accepts two binary digits on inputs, and produces two binary digits, a sum bit and a carry bit on its outputs? serial adder full-adder parallel adder half-adder 8 / 24 Category: Combinational Logic Design 8. In which of the following adder circuits is the carry ripple delay eliminated? carry-look-ahead adder half-adder parallel adder full-adder 9 / 24 Category: Combinational Logic Design 9. To secure a higher speed of addition, which of the following is the preferred solution? serial adder full-adder adder with a look-ahead-carry parallel adder 10 / 24 Category: Combinational Logic Design 10. The adder preferred for applications where circuit minimization is more important than speedis half-adder parallel adder serial adder full-adder 11 / 24 Category: Combinational Logic Design 11. In a digital system BCD arithmetic is preferred to normal binary arithmetic because of ease of operation when input is in BCD format and the output display is decimal BCD arithmetic circuits are less expensive than binary arithmetic circuits BCD arithmetic circuits are simpler than binary arithmetic circuits BCD arithmetic circuits are faster than binary arithmetic circuits 12 / 24 Category: Combinational Logic Design 12. The minimum number of 2-input NOR gates required to realize a full-subtractor is 8 12 9 10 13 / 24 Category: Combinational Logic Design 13. The difference output in a full-subtractor is the same as the sum output of a full-adder carry output of a full-adder difference output of a half-subtractor sum output of a half-adder 14 / 24 Category: Combinational Logic Design 14. In BCD addition, 0110 is required to be added to the sum for getting the correct result, if a carry is produced the sum of two BCD numbers is not a valid BCD number the suni of two BCD numbers is not a valid BCD number or a carry is produced none of these 15 / 24 Category: Combinational Logic Design 15. How many inputs and outputs does a full-adder have? two inputs, one output two inputs, two outputs two inputs, three outputs three inputs, two outputs 16 / 24 Category: Combinational Logic Design 16. The minimum number of 2-input NAND/NOR gates required to realize a half-adder is 4 6 5 3 17 / 24 Category: Combinational Logic Design 17. How many full-adders are required to construct an m-bit parallel adder? m m/2 m-1 m+ 1 18 / 24 Category: Combinational Logic Design 18. A logic circuit that responds to just one input, in accordance with some priority system, among those that may be simultaneously high is called a priority encoder an encode a decoder a priority decoder 19 / 24 Category: Combinational Logic Design 19. The minimum number of 2-input NAND gates required to realize a full adder/full-subtractor is 6 3 5 4 20 / 24 Category: Combinational Logic Design 20. A full-adder can be realized using two half-adders, two OR gates two half-adders, one OR gate one half-adder, two OR gates two half-adders, one AND gate 21 / 24 Category: Combinational Logic Design 21. Parallel adders are combinational logic circuits none of these Both sequential logic circuits 22 / 24 Category: Combinational Logic Design 22. Which logic gate is a basic comparator? X-NOR gate X-OR gate NAND gate NOR gate 23 / 24 Category: Combinational Logic Design 23. The logic gate used in parity checkers is NOR gate X-NOR gate NAND gate X-OR gate 24 / 24 Category: Combinational Logic Design 24. How many inputs and outputs does a full-subtractor circuit have? three inputs, two outputs two inputs, one output two inputs, two outputs two inputs, three outputs Your score is The average score is 4% LinkedIn Facebook Twitter VKontakte 0% Restart quiz Exit Send feedback Share this