HomeElectronics Multiple choice question MCQ online testCombinational Logic Design MCQ {part2} Combinational Logic Design MCQ {part2} Leave a Comment / Electronics Multiple choice question MCQ online test Spread the love 0% 0 votes, 0 avg 8 Created on June 12, 2023Digital electronics Combinational Logic Design {part 2} 1 / 24 Category: Combinational Logic Design 1. A parallel adder in which the carry-out of each full-adder is the carry-in to the next significant digit adder is called a a) parallel carry adder b) ripple carry adder c) serial carry adder d) look-ahead-carry adder 2 / 24 Category: Combinational Logic Design 2. A serial adder requires only one a) counter b) multiplexer c) full-adde d) half-adder 3 / 24 Category: Combinational Logic Design 3. A full-adder can be realized using a) two half-adders, two OR gates b) one half-adder, two OR gates c) two half-adders, one AND gate d) two half-adders, one OR gate 4 / 24 Category: Combinational Logic Design 4. The difference output in a full-subtractor is the same as the a) sum output of a half-adder b) carry output of a full-adder c) sum output of a full-adder d) difference output of a half-subtractor 5 / 24 Category: Combinational Logic Design 5. Which logic gate is a basic comparator? a) NOR gate b) NAND gate c) X-NOR gate d) X-OR gate 6 / 24 Category: Combinational Logic Design 6. In a digital system BCD arithmetic is preferred to normal binary arithmetic because a) of ease of operation when input is in BCD format and the output display is decimal b) BCD arithmetic circuits are less expensive than binary arithmetic circuits c) BCD arithmetic circuits are faster than binary arithmetic circuits d) BCD arithmetic circuits are simpler than binary arithmetic circuits 7 / 24 Category: Combinational Logic Design 7. A device whose inputs are decimal digits and/or alphabetic characters and whose outputs are the coded representations of those inputs is called a) a decode b) a code converter c) an encoder d) a decimal converter 8 / 24 Category: Combinational Logic Design 8. In which of the following adder circuits is the carry ripple delay eliminated? a) full-adder b) half-adder c) parallel adder d) carry-look-ahead adder 9 / 24 Category: Combinational Logic Design 9. In digital systems subtraction is performed a) using half-subtractors b) by none of these c) using adders with 1’s complement representation of negative numbers d) using half-adders 10 / 24 Category: Combinational Logic Design 10. The minimum number of 2-input NAND/NOR gates required to realize a half-adder is a) 3 b) 6 c) 4 d) 5 11 / 24 Category: Combinational Logic Design 11. The minimum number of 2-input NAND gates required to realize a full adder/full-subtractor is a) 6 b) 3 c) 5 d) 4 12 / 24 Category: Combinational Logic Design 12. In BCD addition, 0110 is required to be added to the sum for getting the correct result, if a) none of these b) a carry is produced c) the sum of two BCD numbers is not a valid BCD number d) the suni of two BCD numbers is not a valid BCD number or a carry is produced 13 / 24 Category: Combinational Logic Design 13. The minimum number of 2-input NOR gates required to realize a full-subtractor is a) 9 b) 10 c) 12 d) 8 14 / 24 Category: Combinational Logic Design 14. How many full-adders are required to construct an m-bit parallel adder? a) m+ 1 b) m/2 c) m-1 d) m 15 / 24 Category: Combinational Logic Design 15. BCD subtraction is performed by using a) 1’s complement representation b) S’s complement representation c) 2’s complement representation d) 9’s complement representation 16 / 24 Category: Combinational Logic Design 16. To secure a higher speed of addition, which of the following is the preferred solution? a) adder with a look-ahead-carry b) serial adder c) parallel adder d) full-adder 17 / 24 Category: Combinational Logic Design 17. How many inputs and outputs does a full-adder have? a) two inputs, three outputs b) two inputs, one output c) three inputs, two outputs d) two inputs, two outputs 18 / 24 Category: Combinational Logic Design 18. A logic circuit that responds to just one input, in accordance with some priority system, among those that may be simultaneously high is called a) a decoder b) a priority encoder c) a priority decoder d) an encode 19 / 24 Category: Combinational Logic Design 19. The minimum number of 2-input NAND/NOR gates required to realize a half-subtractor is a) 5 b) 3 c) 6 d) 4 20 / 24 Category: Combinational Logic Design 20. The adder preferred for applications where circuit minimization is more important than speed is a) serial adder b) parallel adder c) half-adder d) full-adder 21 / 24 Category: Combinational Logic Design 21. Which of the following logic circuits accepts two binary digits on inputs, and produces two binary digits, a sum bit and a carry bit on its outputs? a) parallel adder b) full-adder c) serial adder d) half-adder 22 / 24 Category: Combinational Logic Design 22. Parallel adders are a) none of these b) sequential logic circuits c) combinational logic circuits d) Both 23 / 24 Category: Combinational Logic Design 23. How many inputs and outputs does a full-subtractor circuit have? a) two inputs, three outputs b) two inputs, one output c) three inputs, two outputs d) two inputs, two outputs 24 / 24 Category: Combinational Logic Design 24. The logic gate used in parity checkers is a) NOR gate b) X-OR gate c) X-NOR gate d) NAND gate Your score isThe average score is 15% LinkedIn Facebook VKontakte 0% Restart quiz Exit Thank you Send feedback Spread the love
