HomeElectronics Multiple choice question MCQ online testCombinational Logic Design MCQ {part2} Combinational Logic Design MCQ {part2} Leave a Comment / Electronics Multiple choice question MCQ online test Share this 0% 0 votes, 0 avg 6 Created on June 12, 2023Digital electronics Combinational Logic Design {part 2} 1 / 24 Category: Combinational Logic Design 1. In BCD addition, 0110 is required to be added to the sum for getting the correct result, if a) none of these b) a carry is produced c) the sum of two BCD numbers is not a valid BCD number d) the suni of two BCD numbers is not a valid BCD number or a carry is produced 2 / 24 Category: Combinational Logic Design 2. The minimum number of 2-input NAND/NOR gates required to realize a half-adder is a) 4 b) 3 c) 5 d) 6 3 / 24 Category: Combinational Logic Design 3. How many inputs and outputs does a full-subtractor circuit have? a) two inputs, one output b) two inputs, three outputs c) two inputs, two outputs d) three inputs, two outputs 4 / 24 Category: Combinational Logic Design 4. In which of the following adder circuits is the carry ripple delay eliminated? a) carry-look-ahead adder b) full-adder c) half-adder d) parallel adder 5 / 24 Category: Combinational Logic Design 5. A full-adder can be realized using a) two half-adders, two OR gates b) two half-adders, one OR gate c) two half-adders, one AND gate d) one half-adder, two OR gates 6 / 24 Category: Combinational Logic Design 6. BCD subtraction is performed by using a) 2’s complement representation b) 1’s complement representation c) 9’s complement representation d) S’s complement representation 7 / 24 Category: Combinational Logic Design 7. The logic gate used in parity checkers is a) NOR gate b) X-OR gate c) NAND gate d) X-NOR gate 8 / 24 Category: Combinational Logic Design 8. The difference output in a full-subtractor is the same as the a) sum output of a full-adder b) sum output of a half-adder c) carry output of a full-adder d) difference output of a half-subtractor 9 / 24 Category: Combinational Logic Design 9. A logic circuit that responds to just one input, in accordance with some priority system, among those that may be simultaneously high is called a) a priority decoder b) a priority encoder c) a decoder d) an encode 10 / 24 Category: Combinational Logic Design 10. Which of the following logic circuits accepts two binary digits on inputs, and produces two binary digits, a sum bit and a carry bit on its outputs? a) full-adder b) serial adder c) half-adder d) parallel adder 11 / 24 Category: Combinational Logic Design 11. Which logic gate is a basic comparator? a) NOR gate b) NAND gate c) X-OR gate d) X-NOR gate 12 / 24 Category: Combinational Logic Design 12. The minimum number of 2-input NAND gates required to realize a full adder/full-subtractor is a) 6 b) 3 c) 5 d) 4 13 / 24 Category: Combinational Logic Design 13. A serial adder requires only one a) full-adde b) half-adder c) multiplexer d) counter 14 / 24 Category: Combinational Logic Design 14. In a digital system BCD arithmetic is preferred to normal binary arithmetic because a) BCD arithmetic circuits are less expensive than binary arithmetic circuits b) BCD arithmetic circuits are simpler than binary arithmetic circuits c) BCD arithmetic circuits are faster than binary arithmetic circuits d) of ease of operation when input is in BCD format and the output display is decimal 15 / 24 Category: Combinational Logic Design 15. Parallel adders are a) none of these b) sequential logic circuits c) Both d) combinational logic circuits 16 / 24 Category: Combinational Logic Design 16. A parallel adder in which the carry-out of each full-adder is the carry-in to the next significant digit adder is called a a) serial carry adder b) look-ahead-carry adder c) ripple carry adder d) parallel carry adder 17 / 24 Category: Combinational Logic Design 17. How many full-adders are required to construct an m-bit parallel adder? a) m-1 b) m c) m+ 1 d) m/2 18 / 24 Category: Combinational Logic Design 18. In digital systems subtraction is performed a) using half-subtractors b) by none of these c) using half-adders d) using adders with 1’s complement representation of negative numbers 19 / 24 Category: Combinational Logic Design 19. How many inputs and outputs does a full-adder have? a) two inputs, two outputs b) two inputs, three outputs c) two inputs, one output d) three inputs, two outputs 20 / 24 Category: Combinational Logic Design 20. A device whose inputs are decimal digits and/or alphabetic characters and whose outputs are the coded representations of those inputs is called a) an encoder b) a code converter c) a decimal converter d) a decode 21 / 24 Category: Combinational Logic Design 21. The adder preferred for applications where circuit minimization is more important than speedis a) serial adder b) parallel adder c) full-adder d) half-adder 22 / 24 Category: Combinational Logic Design 22. To secure a higher speed of addition, which of the following is the preferred solution? a) adder with a look-ahead-carry b) full-adder c) serial adder d) parallel adder 23 / 24 Category: Combinational Logic Design 23. The minimum number of 2-input NAND/NOR gates required to realize a half-subtractor is a) 3 b) 6 c) 4 d) 5 24 / 24 Category: Combinational Logic Design 24. The minimum number of 2-input NOR gates required to realize a full-subtractor is a) 12 b) 8 c) 10 d) 9 Your score isThe average score is 11% LinkedIn Facebook VKontakte 0% Restart quiz Exit Thank you Send feedback Share this
