HomeElectronics Multiple choice question MCQ online testCombinational Logic Design MCQ Quiz {part1} Combinational Logic Design MCQ Quiz {part1} 2 Comments / Electronics Multiple choice question MCQ online test Share this 0% 0 votes, 0 avg 8 Created on November 12, 2022Digital electronics Combinational Logic Design {Part 1} 1 / 23 Category: Combinational Logic Design 1. A MUX with its address bits generated by a counter operates as a a. modified multiplexer b. serial-to-parallel converter c. parallel-to-serial converter d. modified counter 2 / 23 Category: Combinational Logic Design 2. A logic circuit that converts an n-input binary code into a corresponding single numeric output is called a. an encoder b. a code converter c. a decoder d. a converter 3 / 23 Category: Combinational Logic Design 3. In the hexadecimal to binary priority encoder a. 0 (hex) has the highest priority b. F (hex) has the lowest priority c. F (hex) has the highest priority d. 7 (hex) has the lowest priority 4 / 23 Category: Combinational Logic Design 4. Selection of the input with the higher priority by an encoder is called a. none of these b. input selection c. arbitration d. priority selection 5 / 23 Category: Combinational Logic Design 5. A 4-variable logic circuit can be designed using a. two 8:1 multiplexers and one 2:1 multiplexer b. an 8:1 multiplexer and one inverter c. a 16:1 multiplexer d. any of these 6 / 23 Category: Combinational Logic Design 6. A binary-to-octal decoder is a a. any lines-to-8 line decoder b. 3-line to 8-line decoder c. 4-line to 8-line decoder d. 1-line to 8-line decoder 7 / 23 Category: Combinational Logic Design 7. The number of 1:16 demultiplexers required for designing a 4-output 4-variable combinational circuit is a. 16 b. 4 c. 1 d. 8 8 / 23 Category: Combinational Logic Design 8. A multiplexer with four select bits is a a. 16:1 multiplexer b. 32:1 multiplexer c. 4:1 multiplexer d. 8:1 multiplexer 9 / 23 Category: Combinational Logic Design 9. A multiplexer is also known as a. a data restorer b. a data selector c. a data distributor d. a data accumulator 10 / 23 Category: Combinational Logic Design 10. A logic circuit that accepts several data inputs and allows only one of them at a time to get through to the output is called a. a receiver b. a multiplexer c. a transmitter d. a demultiplexer 11 / 23 Category: Combinational Logic Design 11. A BCD-to-decimal decoder is a. a 3-line to 8-line decoder b. any lines to 10-lines decode c. a 1-line to 10-line decoder d. a 4-line to 10-line decoder 12 / 23 Category: Combinational Logic Design 12. A Demultiplexer is used to a. select data from several inputs and route it to a single output b. perform arithmetic division c. steer the data from a single input to one of the many outputs d. perform parity checking 13 / 23 Category: Combinational Logic Design 13. A 16:1 multiplexer can be used to design a. 4 variable logic function b. BCD to binary code converter c. BCD to 7 segment decoder d. full-adder 14 / 23 Category: Combinational Logic Design 14. ABCD to XS-3 code converter can be designed using a. a 1:16 de multiplexer b. none of these c. a 16:1 multiplexer d. two 16:1 multiplexers 15 / 23 Category: Combinational Logic Design 15. Which of the following logic circuits takes data from a single source and distributes it to one of several output lines? a. multiplexer b. decoder c. demultiplexer d. encoder 16 / 23 Category: Combinational Logic Design 16. A combinational logic circuit which is used to send data coming from a single source to two or more separate destinations is called a. a multiplexer b. a demultiplexer c. a decoder d. an encoder 17 / 23 Category: Combinational Logic Design 17. A demultiplexer with 4-bit select input has a. one data input and eight data output lines b. one data input and four data output lines c. one data input and sixteen data output lines d. one data input and ten data output lines 18 / 23 Category: Combinational Logic Design 18. Selection of the input with the higher priority by an encoder is called a. priority selection b. none of these c. input selection d. arbitration 19 / 23 Category: Combinational Logic Design 19. A 32:1 mux can be designed using a. two 16:1 muxs and two two-input OR gates b. two 16:1 muxs and one two input AND gate c. two 16:1 muxs and one two input OR gate d. two 16:1 muxs only 20 / 23 Category: Combinational Logic Design 20. What is the largest number of data inputs which a data selector with two control inputs can handle? a. 16 b. 4 c. 8 d. 2 21 / 23 Category: Combinational Logic Design 21. Which logic device is called a distributor? a. decoder b. multiplexer c. encoder d. demultiplexer 22 / 23 Category: Combinational Logic Design 22. The number of 4-line-to-16-line decoders required to make an 8-line-to-256-line decoder is a. 64 b. 17 c. 32 d. 16 23 / 23 Category: Combinational Logic Design 23. The number of 3-line-to-8-line decoders required for selecting 1 out of 64 is a. 8 b. 4 c. 9 d. 16 Your score isThe average score is 18% LinkedIn Facebook VKontakte 0% Restart quiz Exit Thank you Send feedback Share this
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