HomeElectronics Multiple choice question MCQ online testCombinational Logic Design MCQ Quiz {part1} Combinational Logic Design MCQ Quiz {part1} 2 Comments / Electronics Multiple choice question MCQ online test Spread the love 0% 0 votes, 0 avg 8 Created on November 12, 2022Digital electronics Combinational Logic Design {Part 1} 1 / 23 Category: Combinational Logic Design 1. A 32:1 mux can be designed using a. two 16:1 muxs only b. two 16:1 muxs and one two input OR gate c. two 16:1 muxs and one two input AND gate d. two 16:1 muxs and two two-input OR gates 2 / 23 Category: Combinational Logic Design 2. Selection of the input with the higher priority by an encoder is called a. arbitration b. none of these c. input selection d. priority selection 3 / 23 Category: Combinational Logic Design 3. A multiplexer with four select bits is a a. 16:1 multiplexer b. 4:1 multiplexer c. 32:1 multiplexer d. 8:1 multiplexer 4 / 23 Category: Combinational Logic Design 4. A demultiplexer with 4-bit select input has a. one data input and eight data output lines b. one data input and ten data output lines c. one data input and four data output lines d. one data input and sixteen data output lines 5 / 23 Category: Combinational Logic Design 5. Which of the following logic circuits takes data from a single source and distributes it to one of several output lines? a. multiplexer b. encoder c. decoder d. demultiplexer 6 / 23 Category: Combinational Logic Design 6. A 4-variable logic circuit can be designed using a. an 8:1 multiplexer and one inverter b. any of these c. two 8:1 multiplexers and one 2:1 multiplexer d. a 16:1 multiplexer 7 / 23 Category: Combinational Logic Design 7. The number of 3-line-to-8-line decoders required for selecting 1 out of 64 is a. 16 b. 9 c. 4 d. 8 8 / 23 Category: Combinational Logic Design 8. What is the largest number of data inputs which a data selector with two control inputs can handle? a. 2 b. 16 c. 8 d. 4 9 / 23 Category: Combinational Logic Design 9. A logic circuit that converts an n-input binary code into a corresponding single numeric output is called a. an encoder b. a decoder c. a code converter d. a converter 10 / 23 Category: Combinational Logic Design 10. A binary-to-octal decoder is a a. any lines-to-8 line decoder b. 4-line to 8-line decoder c. 1-line to 8-line decoder d. 3-line to 8-line decoder 11 / 23 Category: Combinational Logic Design 11. A 16:1 multiplexer can be used to design a. 4 variable logic function b. BCD to 7 segment decoder c. full-adder d. BCD to binary code converter 12 / 23 Category: Combinational Logic Design 12. Which logic device is called a distributor? a. decoder b. encoder c. demultiplexer d. multiplexer 13 / 23 Category: Combinational Logic Design 13. A combinational logic circuit which is used to send data coming from a single source to two or more separate destinations is called a. a decoder b. a multiplexer c. an encoder d. a demultiplexer 14 / 23 Category: Combinational Logic Design 14. A logic circuit that accepts several data inputs and allows only one of them at a time to get through to the output is called a. a transmitter b. a demultiplexer c. a receiver d. a multiplexer 15 / 23 Category: Combinational Logic Design 15. The number of 1:16 demultiplexers required for designing a 4-output 4-variable combinational circuit is a. 1 b. 4 c. 8 d. 16 16 / 23 Category: Combinational Logic Design 16. A MUX with its address bits generated by a counter operates as a a. modified multiplexer b. modified counter c. parallel-to-serial converter d. serial-to-parallel converter 17 / 23 Category: Combinational Logic Design 17. A multiplexer is also known as a. a data selector b. a data distributor c. a data accumulator d. a data restorer 18 / 23 Category: Combinational Logic Design 18. ABCD to XS-3 code converter can be designed using a. a 1:16 de multiplexer b. none of these c. two 16:1 multiplexers d. a 16:1 multiplexer 19 / 23 Category: Combinational Logic Design 19. Selection of the input with the higher priority by an encoder is called a. arbitration b. none of these c. input selection d. priority selection 20 / 23 Category: Combinational Logic Design 20. In the hexadecimal to binary priority encoder a. 7 (hex) has the lowest priority b. 0 (hex) has the highest priority c. F (hex) has the lowest priority d. F (hex) has the highest priority 21 / 23 Category: Combinational Logic Design 21. A Demultiplexer is used to a. perform parity checking b. perform arithmetic division c. steer the data from a single input to one of the many outputs d. select data from several inputs and route it to a single output 22 / 23 Category: Combinational Logic Design 22. A BCD-to-decimal decoder is a. a 4-line to 10-line decoder b. a 1-line to 10-line decoder c. any lines to 10-lines decode d. a 3-line to 8-line decoder 23 / 23 Category: Combinational Logic Design 23. The number of 4-line-to-16-line decoders required to make an 8-line-to-256-line decoder is a. 32 b. 17 c. 64 d. 16 Your score isThe average score is 18% LinkedIn Facebook VKontakte 0% Restart quiz Exit Thank you Send feedback Spread the love
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