HomeElectronics Multiple choice question MCQ online testCombinational Logic Design MCQ Quiz {part1} Combinational Logic Design MCQ Quiz {part1} 2 Comments / Electronics Multiple choice question MCQ online test Spread the love 0% 0 votes, 0 avg 10 Created on November 12, 2022Digital electronics Combinational Logic Design {Part 1} 1 / 23 Category: Combinational Logic Design 1. What is the largest number of data inputs which a data selector with two control inputs can handle? a. 16 b. 8 c. 2 d. 4 2 / 23 Category: Combinational Logic Design 2. A logic circuit that accepts several data inputs and allows only one of them at a time to get through to the output is called a. a receiver b. a multiplexer c. a transmitter d. a demultiplexer 3 / 23 Category: Combinational Logic Design 3. The number of 4-line-to-16-line decoders required to make an 8-line-to-256-line decoder is a. 32 b. 16 c. 64 d. 17 4 / 23 Category: Combinational Logic Design 4. A combinational logic circuit which is used to send data coming from a single source to two or more separate destinations is called a. a multiplexer b. a demultiplexer c. a decoder d. an encoder 5 / 23 Category: Combinational Logic Design 5. The number of 3-line-to-8-line decoders required for selecting 1 out of 64 is a. 8 b. 16 c. 9 d. 4 6 / 23 Category: Combinational Logic Design 6. A 4-variable logic circuit can be designed using a. a 16:1 multiplexer b. any of these c. an 8:1 multiplexer and one inverter d. two 8:1 multiplexers and one 2:1 multiplexer 7 / 23 Category: Combinational Logic Design 7. Which of the following logic circuits takes data from a single source and distributes it to one of several output lines? a. encoder b. demultiplexer c. multiplexer d. decoder 8 / 23 Category: Combinational Logic Design 8. A Demultiplexer is used to a. steer the data from a single input to one of the many outputs b. select data from several inputs and route it to a single output c. perform arithmetic division d. perform parity checking 9 / 23 Category: Combinational Logic Design 9. A multiplexer with four select bits is a a. 8:1 multiplexer b. 4:1 multiplexer c. 16:1 multiplexer d. 32:1 multiplexer 10 / 23 Category: Combinational Logic Design 10. A 16:1 multiplexer can be used to design a. BCD to 7 segment decoder b. BCD to binary code converter c. full-adder d. 4 variable logic function 11 / 23 Category: Combinational Logic Design 11. A MUX with its address bits generated by a counter operates as a a. modified multiplexer b. serial-to-parallel converter c. parallel-to-serial converter d. modified counter 12 / 23 Category: Combinational Logic Design 12. A binary-to-octal decoder is a a. any lines-to-8 line decoder b. 1-line to 8-line decoder c. 3-line to 8-line decoder d. 4-line to 8-line decoder 13 / 23 Category: Combinational Logic Design 13. Which logic device is called a distributor? a. encoder b. decoder c. demultiplexer d. multiplexer 14 / 23 Category: Combinational Logic Design 14. The number of 1:16 demultiplexers required for designing a 4-output 4-variable combinational circuit is a. 16 b. 8 c. 1 d. 4 15 / 23 Category: Combinational Logic Design 15. ABCD to XS-3 code converter can be designed using a. none of these b. a 1:16 de multiplexer c. two 16:1 multiplexers d. a 16:1 multiplexer 16 / 23 Category: Combinational Logic Design 16. A logic circuit that converts an n-input binary code into a corresponding single numeric output is called a. a decoder b. an encoder c. a converter d. a code converter 17 / 23 Category: Combinational Logic Design 17. Selection of the input with the higher priority by an encoder is called a. priority selection b. arbitration c. input selection d. none of these 18 / 23 Category: Combinational Logic Design 18. Selection of the input with the higher priority by an encoder is called a. priority selection b. input selection c. none of these d. arbitration 19 / 23 Category: Combinational Logic Design 19. In the hexadecimal to binary priority encoder a. F (hex) has the highest priority b. 7 (hex) has the lowest priority c. 0 (hex) has the highest priority d. F (hex) has the lowest priority 20 / 23 Category: Combinational Logic Design 20. A BCD-to-decimal decoder is a. any lines to 10-lines decode b. a 4-line to 10-line decoder c. a 1-line to 10-line decoder d. a 3-line to 8-line decoder 21 / 23 Category: Combinational Logic Design 21. A multiplexer is also known as a. a data distributor b. a data selector c. a data restorer d. a data accumulator 22 / 23 Category: Combinational Logic Design 22. A 32:1 mux can be designed using a. two 16:1 muxs and one two input AND gate b. two 16:1 muxs and two two-input OR gates c. two 16:1 muxs only d. two 16:1 muxs and one two input OR gate 23 / 23 Category: Combinational Logic Design 23. A demultiplexer with 4-bit select input has a. one data input and four data output lines b. one data input and sixteen data output lines c. one data input and ten data output lines d. one data input and eight data output lines Your score isThe average score is 20% LinkedIn Facebook VKontakte 0% Restart quiz Exit Thank you Send feedback Spread the love
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