HomeElectronics Multiple choice question MCQ online testCombinational Logic Design MCQ Quiz {part1} Combinational Logic Design MCQ Quiz {part1} 2 Comments / Electronics Multiple choice question MCQ online test Share this 0% 0 votes, 0 avg 8 Created on November 12, 2022Digital electronics Combinational Logic Design {Part 1} 1 / 23 Category: Combinational Logic Design 1. Selection of the input with the higher priority by an encoder is called a. none of these b. input selection c. arbitration d. priority selection 2 / 23 Category: Combinational Logic Design 2. A logic circuit that accepts several data inputs and allows only one of them at a time to get through to the output is called a. a transmitter b. a demultiplexer c. a receiver d. a multiplexer 3 / 23 Category: Combinational Logic Design 3. A binary-to-octal decoder is a a. 3-line to 8-line decoder b. 4-line to 8-line decoder c. 1-line to 8-line decoder d. any lines-to-8 line decoder 4 / 23 Category: Combinational Logic Design 4. A Demultiplexer is used to a. steer the data from a single input to one of the many outputs b. select data from several inputs and route it to a single output c. perform arithmetic division d. perform parity checking 5 / 23 Category: Combinational Logic Design 5. A 16:1 multiplexer can be used to design a. BCD to 7 segment decoder b. full-adder c. 4 variable logic function d. BCD to binary code converter 6 / 23 Category: Combinational Logic Design 6. The number of 4-line-to-16-line decoders required to make an 8-line-to-256-line decoder is a. 64 b. 17 c. 32 d. 16 7 / 23 Category: Combinational Logic Design 7. The number of 1:16 demultiplexers required for designing a 4-output 4-variable combinational circuit is a. 4 b. 8 c. 16 d. 1 8 / 23 Category: Combinational Logic Design 8. A 4-variable logic circuit can be designed using a. two 8:1 multiplexers and one 2:1 multiplexer b. a 16:1 multiplexer c. any of these d. an 8:1 multiplexer and one inverter 9 / 23 Category: Combinational Logic Design 9. Selection of the input with the higher priority by an encoder is called a. input selection b. arbitration c. priority selection d. none of these 10 / 23 Category: Combinational Logic Design 10. A logic circuit that converts an n-input binary code into a corresponding single numeric output is called a. a converter b. an encoder c. a decoder d. a code converter 11 / 23 Category: Combinational Logic Design 11. A combinational logic circuit which is used to send data coming from a single source to two or more separate destinations is called a. a decoder b. an encoder c. a multiplexer d. a demultiplexer 12 / 23 Category: Combinational Logic Design 12. The number of 3-line-to-8-line decoders required for selecting 1 out of 64 is a. 8 b. 9 c. 16 d. 4 13 / 23 Category: Combinational Logic Design 13. What is the largest number of data inputs which a data selector with two control inputs can handle? a. 2 b. 4 c. 8 d. 16 14 / 23 Category: Combinational Logic Design 14. A demultiplexer with 4-bit select input has a. one data input and four data output lines b. one data input and ten data output lines c. one data input and eight data output lines d. one data input and sixteen data output lines 15 / 23 Category: Combinational Logic Design 15. Which of the following logic circuits takes data from a single source and distributes it to one of several output lines? a. multiplexer b. demultiplexer c. decoder d. encoder 16 / 23 Category: Combinational Logic Design 16. A MUX with its address bits generated by a counter operates as a a. modified counter b. serial-to-parallel converter c. modified multiplexer d. parallel-to-serial converter 17 / 23 Category: Combinational Logic Design 17. Which logic device is called a distributor? a. encoder b. decoder c. multiplexer d. demultiplexer 18 / 23 Category: Combinational Logic Design 18. A 32:1 mux can be designed using a. two 16:1 muxs and two two-input OR gates b. two 16:1 muxs and one two input OR gate c. two 16:1 muxs and one two input AND gate d. two 16:1 muxs only 19 / 23 Category: Combinational Logic Design 19. A multiplexer with four select bits is a a. 4:1 multiplexer b. 32:1 multiplexer c. 16:1 multiplexer d. 8:1 multiplexer 20 / 23 Category: Combinational Logic Design 20. ABCD to XS-3 code converter can be designed using a. two 16:1 multiplexers b. none of these c. a 1:16 de multiplexer d. a 16:1 multiplexer 21 / 23 Category: Combinational Logic Design 21. A BCD-to-decimal decoder is a. any lines to 10-lines decode b. a 1-line to 10-line decoder c. a 4-line to 10-line decoder d. a 3-line to 8-line decoder 22 / 23 Category: Combinational Logic Design 22. A multiplexer is also known as a. a data accumulator b. a data distributor c. a data selector d. a data restorer 23 / 23 Category: Combinational Logic Design 23. In the hexadecimal to binary priority encoder a. 7 (hex) has the lowest priority b. F (hex) has the highest priority c. F (hex) has the lowest priority d. 0 (hex) has the highest priority Your score isThe average score is 18% LinkedIn Facebook Twitter VKontakte 0% Restart quiz Exit Thank you Send feedback Share this
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