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Flip flops
Flip Flop is a digital device that has the capability to store 1bit binary data at a time. The flip flop is a sequential bistable circuit that has two stable states. Flip flop is a circuit that maintains a state on its output until the input signal changes. FlipFlops are the basic element to build the digital electronics system or devices such as computers and different communication devices. They are the basic storage element of any data storage. The data stored in flipflop can be changed by varying the input.
Types of flipflop

SR or RS FlipFlop

D FlipFlop

JK FlipFlop

T FlipFlop
The two states of a flipflop represented by “zero” and “one”.
Input and output of FlipFlop
Input is given at the Q_{n} and the output also gets on the same point Q_{n}. But the output is denoted by Q_{n+1}. 1 is actually the nth iteration of the cycle. Because FLIPFLOP is a memory element and this stores data so the next iteration of the cycle is named Q_{n+1}. Input and output are at the same point Q_{n}. Q_{n }Bar is the complement of Q_{n} and for the valid operation of FlipFlop, it should be a complement of Qn. complement means if Q_{n} is 0 then the Q_{n} bar is 1 and when Q_{n} is 1 then the Q_{n}bar is 0.
Here we put the input at the point of Q_{n} and output qn+1 also we get on the same point. R and S is also input pins but really these are control pins. R means Reset and s means Set. Both control pins are used to what mode we want to function performed in flip flop. R and S pins are used to control the mode of operation.
SR flip flop using NOR gate
A simple one bit RS Flip Flops are made by using two crosscoupled NOR gates connected in the same configuration. The SR (SetReset) flipflop is one of the simplest sequential circuit. The RS Flip Flop is considered as one of the most basic sequential logic circuits.
Now we make Reset pin 1 and take Q_{n} is zero then functionality we see that output Q_{n+1} is zero.
If Q_{n} is 1 then we see that output q_{n+1} is also zero. So we see that when the reset pin is 1 then the output is always zero weather input at Q_{n} is o or 1. In this mode flip flop makes all input values reset and it will not work as a memory element.
When the Set input pin is 1 and the Reset pin is zero then we see the functionality. First, we check the input value Q_{n} is zero. The output is 1. And when take the input value at Q_{n} is zero then the output is also 1 at Q_{n+1}. So we see that when the set pin is 1 and the reset pin is 0 then the output will always 1 in these cases.
Here, we use NOR gates to implement the R S Flipflop circuit. implementation of R S flipflop can be implemented using NAND gate.
When the clock value is zero and input at both R and S pin is zero then, In this mode, the output is the same as the input value. R and S input can be connected directed but the reason the connection through AND gate is to make FlipFlop enable or disable. If the clock signal is high or 1 then the AND gate can give output High if any one of AND gate pin is high, in the Clock High or 1, the flipFlop is in Enable condition but if the clk is LOW means flipflop will disable because if even one input of AND gate is ) then the AND gate will give 0 output. So these inputs called the control input pins.
Operation
First condition when R and S both are 0, Clk pin is High in the whole operation to enable. R and S both are 0 and clk is 1 so AND gate will give 0, Now put Q_{n}=0, this 0 goes to NOR gate and both pins of NOR gate will 0 so the output at Q_{n} Bar is 1. This 1 is now going to the Upper NOR gate and because one pin of this NOR gate is 0, the output will 0. And this operation will be continued.
S=0, R=0, Q_{n}=0, Q_{n+1}=0
S=0, R=0, Q_{n}=1, Q_{n+1}= 1
Next conditionS(SET) is 0 and R (RESET) is 1. one AND gate give output 1 and the second AND gate gives 0. Now, when Q_{n}=0 we take. the 0 goes to the NOR gate and both pins is 0 of the NOR input gate will give 1 output at Q_{n}Bar, This 1 goes to (upper) NOR gate, and here both inputs of NOR gate is 1 and this gives the output 0, and again this zero will go to Nor gate and give Q_{n}Bar 1 and this process continuously operated.
S=0
R=1
Q_{n}=0
Q_{n+1}=0
S=0, R=1, Q_{n}= 0, Q_{n+1}= 0
S=0, R=1, Q_{n}= 0, Q_{n+1}= 1
S=1, R=0, Q_{n}= 0, Q_{n+1}= 1
In these operations, we see that when the RESET (R) pin is HIGH then the output Q_{n+1} is always LOW. and when the SET(S) pins are HIGH, the Output will always HIGH.
S=1, R=1, Q_{n}= 0, Q_{n+1}= 0
S=1, R=1, Q_{n}= 1, Q_{n+1}= 0
This is known as the running state of SR flipflop because when both S and R pins are high then the output will only 0 and 0 even Q_{n} value 0 or 1. and not maintain the complementary with Q_{n} and Q_{n}Bar.
Truth Table of SR Flipflop
Function Table and Excitation Table of SR Flipflop
R and S are actually the control pins that control the operation.
d means don’t care means either 0 or 1. Excitation means how we excite the Flipflop for a required output state, Which logic input to be required to a particular output.
JK Flipflop
flop is named after Jack Kilby, an electrical engineer who invented IC. JK FlipFlop is a modified version of an SR flipflop. As we know that in SR flipFlop there is an invalid state when both control inputs S and R are 1 and then the system was going to in race condition. This problem prevented and overcome in the J K Flip Flop. In this no “invalid” or “illegal” output state. The operation of the J_k Flip flop is the same as the RS flip flop.
JK Flip flop diagram using NAND gate
JK FlipFlop using NOR gate
When S and R both pins are 1 then the output given by S R flipflop is invalid, so resolving this problem some hardware circuit conversion made in implementation by using a feedback connection to the input of and gate from the output. And after the changing of implementation S and R will be named by respectively J and K.
All functionality (except both R and S=1) of J K flip flop will same as R S flip flop means when we put the value of Q_{n}= 1 and J and K = 0 then the output Q_{n+1}=0
When J=0, K=1, and input gave is 0 then the output at point Q_{n} is Q_{n+1}=0
And same as RS flip flop all values of output states are the same as RS Flip Flop.
But there was a problem when both R and S pins are 1. So we check here after putting the value Q_{n}=0 . output Q_{n+1} at point Q_{n} we get 1. And when Q_{n}=1, the output value Q_{n+1} will 0. we see that the value of the Q_{n }and Q bar will complement each other means system is not an invalid state or not in a running state.
JK flip flop truth table
Function Table and Excitation Table
Latch– Latches are the basic building blocks using flipflops are constructed. This has the capability to store 1 bit.
Clock signal
The clock signal repeated itself after every “t” second. A clock signal or clock pulse is a type of signal that oscillates between HIGH and LOW States continuously after a particular time delay. Digital circuits rely on clock signals to know when and how to execute the functions that are programmed
State changing in FlipFlop occurred by the only clock signal.
If the output of a flip flop is given by the 1^{st} clock, this is denoted by Q_{n}. But output given by the next clock is given by Q_{n+}_{1}
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