Digital Electronics MCQ

SR, D, and JK flip flops can be used to construct a serial shift register. A T flip – flop gives the output 0 when input 1 is given and gives output 1 when input 0 is given. Thus, it cannot be used as a serial shift register.

Ex – NOR gate is a one – bit comparator as the output for the gate is 1 if similar inputs are given to the gate and output is 0 if different inputs are given to the gate.

Two 2 input AND gates are placed with a NOR – based S – R latch to convert it to an S – R flip – flop. One AND gate is given R in one input and clock in the other. Similarly the second AND gate is given S in one input and clock in the other.

The parity method can help in finding only single errors within a word. The double errors cannot be found as the parity of the bits does not change. If double errors need to be identified, the check – sum method can be used.

Check sum enables to find double errors and also find the erroneous bits. The parity method can help in finding only single errors within a word as a double error will not change the parity bits.

XNOR gate is called coincidence gate and gives 1 if similar inputs are given to the gate and output is 0 if different inputs are given to the gate. XOR gate is called anti – coincidence gate and gives 0 if similar inputs are given to the gate and output is 1 if different inputs are given to the gate.

A circuit is a closed-loop through which electrons can pass. Electrical energy is provided in the circuit by a source of electricity, such as a battery.

 A negative level triggered flip – flop has a NOT gate present between clock input and the input of AND gate. Thus, the negative level triggered flip – flop change its state when the clock is negative.

According to Hamming’s analysis, a minimum distance of 2 is required for single error detection. This Hamming distance represents the number of bits that are changed from one code word to the other.

The MOS logic family uses the MOSFET devices to perform its operation. NAND and NOR are the basic gates that are the building blocks of most digital circuits.

A single flip flop is a divide – by – two device. The frequency of the output from a JK flip – flop, when J = 1, K = 1, and a clock with pulse waveform is given is half the frequency of clock input.

A digital circuit is a circuit that has a signal that must fall into one of two discrete levels. Each level is read as one of two states (on/off, 0/1, true/false, for example). To perform Boolean logic, digital circuits use transistors to generate logic gates.

Toggle operation in Digital Circuits like J – K flip – flop occurs when J = 1 and K = 1. The output toggles between 0 and 1 continuously. This oscillation between 0 and 1 leads to a race – around condition which can be solved using a Master – slave flip flop.

An enable pin allows to activate and deactivate the multiplexer. When enable pin is 0, the output is obtained while when enable pin is 0, the multiplexer is disabled.

A group of 1s in 4 cells of a K – map is called Quad. A group of 1s in 2 cells of a K – map is called Pair and a group of 1s in 8 cells of a K – map is called Octet.

A don’t care condition can take 0 or 1 according to the requirement. SOP expressions may consider it to be 1 to increase the number of 1s and POS expressions may consider it to be 0 to increase the number of 0s.

The input for which the flip flop changes its state when synchronized with the clock is called the synchronous control inputs. For the S – R flip flop, both S and R are synchronous control inputs

Four 4 – bit parallel binary adders along with 16 number of 2 – input AND gates will be required to construct a 4 – bit parallel multiplier. The parallel adders are used to add the partial products which are calculated using the AND gates.

Four 4 – bit parallel binary adders along with 16 number of 2 – input AND gates will be required to construct a 4 – bit parallel multiplier. The AND gate helps in getting the partial products while the parallel – adder are used to add the partial products.

Emitter coupled logic or ECL is a Current – Mode logic. While operating in active mode, they help in eliminating the turn – off delay of saturated transistors. ECL family has a higher switching speed and dissipates more power.

Bipolar IC’s can be classified as saturated and non – saturated logic families. ECL (Emitter – coupled Logic) and Schottky TTL are said to come under the non – saturated logic family.

When the clock is low, the input given to D will have no effect. The set and reset pins of the NAND gates are high. When a NAND gate is given 1 as an input to any of the pins, the output will always be 0.

TTL circuit uses multi – emitter transistors which have a smaller area. The capacitance can be represented in terms of area and distance between the plates using the expressions C = Aε₀/d. As “C” is directly proportional to “A”, a smaller area leads to a lower capacitance.

A clock must be used along with synchronous control inputs to trigger a change in the flip flop. These flip – flops may be edge – triggered or level – triggered. A change should occur only when the clock changes from 0 to 1 or vice versa.

If the gate output is high in a TTL circuit, the current must be given to the input of the gate being driven. Thus, the output must act as a current source. In a normal TTL circuit, about 40μA of current is drawn from the input from a output that is HIGH.

A sequential code is a code where each succeeding code is one binary number more than the preceding code. Thus, 8421 is a sequential code. Sequential codes are useful in manipulating mathematical data.

A reflexive code is a code where the code for 9 is the complement of code for 0 and so on. A sequential code is a code where each succeeding code is one binary number more than the preceding code. Excess – 3 code satisfies both these properties.

Computers, information appliances, digital cameras, digital televisions, flash memory, key USB memory, mobile phones, hard discs, and computer memory devices are examples of digital electronics. After analog signals have been transformed to digital form, digital signal processing is applied to them.

When the clock is low, the input given to D will have no effect. This is because the set and reset pins of the NAND gates are kept high. When HIGH value is given to NAND gates the output result will be zero.

A reflexive code is the one where the code for 9 is the complement of code for 0, code for 8 is the complement of code for 1, and so on. Thus, 2421 and 5211 are reflexive codes.

TTL circuit uses multi – emitter transistors. These transistors have a smaller area. As Capacitance is directly proportional to area, a smaller area leads to a lower capacitance.

The output in a combinational circuit depends on the mixture of input signals present at that moment. It is not determined by the past conditions. The output in a synchronous circuit depends on the mixture of input signals present at that moment and also the past conditions.

In Digital Circuits, a frequency division of 2n of the pulsed clock signal can be obtained by connecting n flip – flops in cascade. Thus, for 4 flip – flops clock frequency can be divided by 16.

Inter–Integrated circuits can be represented by IIC or I2C is also called the Merged Transistor Logic. They use n – p – n or p – n – p transistors to form IC’s.

 In a K – map if a group of 1s in eight cells are present, it makes an Octet. A group of 1s in two cells is called a Pair and a group of 1s in four cells is a Quad.

 The input at which the flip flop changes its state when synchronized with the clock is called the synchronous control inputs. For T flip flop T is the synchronous control input.

 The TTL circuit uses multi – emitter transistors with many emitters in the input. Thus, the number of emitters is determined by the fan – in. Fan – in determines the number of inputs the particular gate can handle

In Digital Electronics, 4 cycles of addition and shifting in a 4 – bit multiplier are required to perform multiplication using the shift method. The multiplicand is copied as a partial product when multiplier bit is 1 and multiplicand is 0 when multiplier bit is 0.

A 4 x 1 multiplexer has 2 select lines, 4 input lines, and 1 output line. AND gates are required to pass the inputs. Thus 4 AND gates will be used for each input. 3 – input AND gate is used, where 2 inputs come from each of the select lines and 1 input for the data.

The results “X + XY = X” and “X(X + Y) = X” follows the absorption law. The expression given can be written in the form X + XY = X(1 + Y). Any value – added with 1 will give 1 itself. Therefore 1 + Y = 1 and X + XY = X.

If the gate output is Low in a TTL digital circuit, the gate must be capable of sinking current drawn from the input of gates. Thus, the output must act as a current sink.

The negative level triggered the flip – flop in Digital Electronics changes its state when the clock is negative. Thus, a negative level triggered flip – flop has a NOT gate present between clock input and the input of AND gate.

Propagation delay represents a function of the switching time of a particular transistor or MOSFET. The propagation delay helps in determining the speed of logic circuits.

According to Hamming’s analysis, a minimum distance of 3 is required for a single error correction. Hamming distance represents the number of bits that change from one code word to the other.

A Ripple – carry adder is a parallel binary adder in which the addition of more than 1 – bit data can be done simultaneously. The inputs to a parallel circuit can be sent and processed at once unlike series circuits in which inputs are sent one by one.

Two 16 x 1 mux will enable to give 32 inputs. The final output can be obtained after passing the output from each 16 x 1 mux through an OR gate. The select lines will help in selecting a particular output.