HomeMCQ-Online test MCQ-Online test quiz 0% Created on July 24, 2023VLSI VLSI (PART 2) nMOS fabrication Hint First in first out (FIFO) technique and finite state machine technique is used in the logic design of the VLSI circuits. 1 / 26 1. ..................... is used in logic design of VLSI. a. LIFO b. FIFO c. FILO d. LILO Hint As the die size shrinks due to scaling, the number of die per wafer increases and the complexity of making the photomasks increases rapidly. 2 / 26 2. As die size shrinks, the complexity of making the photomasks ................... a. increases b. decreases c. remains the same d. cannot be determined Hint Small scale integration has one or more logic gate. Further improved technology is medium scale integration which consists of hundred logic gates. Large scale integration has thousand logic gates. 3 / 26 3. Medium scale integration has ............... a. ten logic gates b. fifty logic gates c. hundred logic gates d. thousands logic gates Hint As photolithography comes closer to the fundamental law of optics, achieving high accuracy in doping concentration becomes difficult, which leads to error due to variation. 4 / 26 4. The difficulty in achieving high doping concentration leads to.................... a. error in concentration b. error in variation c. error in doping d. distribution error 5 / 26 5. Physical and electrical specification is given in ................... a. architectural design b. logic design c. system design d. functional design Hint Contact cuts are made in the desired polysilicon area, source and gate. COntact cuts are those places where connection has to be made. 6 / 26 6. Contact cuts are made in............... a. source b. drain c. metal layer d. diffusion layer Hint In nMOS fabrication, etching is done using hydrofluoric acid or plasma. Etching is a process used to remove layers from the surface. 7 / 26 7. In nMOS fabrication, etching is done using a. plasma b. hydrochloric acid c. sulphuric acid d. sodium chloride 8 / 26 8. The photoresist layer is exposed to........... a. Visible light b. Ultraviolet light c. Infra red light d. LED Hint In nMOS device, the gate material could be metal or polysilicon. This polysilicon layer has heavily doped polysilicon deposited by CVD. 9 / 26 9. In nMOS device, gate material could be a. silicon b. polysilicon c. boron d. phosphorus Hint Very large scale integration is the process of creating an integrated circuit with thousands of transistors into one single chip. 10 / 26 10. VLSI technology uses ......................... to form integrated circuit. a. transistors b. switches c. diodes d. buffers Hint The metal layer is masked and etched to form interconnection pattern. The metal layer was formed using aluminium deposited over the formed surface. 11 / 26 11. Interconnection pattern is made on.................. a. polysilicon layer b. silicon-di-oxide layer c. metal layer d. diffusion layer 12 / 26 12. Which is the commonly used bulk substrate in nMOS fabrication? a. silicon crystal b. silicon-on-sapphire c. phosphorus d. silicon-di-oxide Hint Diffusion is carried out by heating the wafer to high temperature and passing a gas containing the desired ntype impurity. 13 / 26 13. In diffusion process ................... impurity is desired. a. n type b. p type c. np type d. none of the mentioned Hint Above a layer of silicon dioxide which acts as a barrier, an insulating layer is provided upon which other layers may be deposited and patterned. 14 / 26 14. What kind of substrate is provided above the barrier to dopants? a. insulating b. conducting c. silicon d. semiconducting Hint Explanation: nMOS fabrication process is carried out in thin wafer of a single crystal with high purity. 15 / 26 15. nMOS fabrication process is carried out in a. thin wafer of a single crystal b. thin wafer of multiple crystals c. thick wafer of a single crystal d. thick wafer of multiple crystals Hint Problem statement is a high level representation of the system. Performance, functionality and physical dimensions are considered here. 16 / 26 16. Which is the high level representation of VLSI design? a. problem statement b. logic design c. HDL program d. functional design Hint Boron is used to suppress the unwanted conduction between transistor sites. It is implanted in the exposed regions. 17 / 26 17. ......................is used to suppress unwanted conduction. a. phosphorus b. boron c. silicon d. oxygen 18 / 26 18. .................. architecture is used to design VLSI. a. system on a device b. single open circuit c. system on a chip d. system on a circuit Hint In nMOS device, the gate material could be metal or polysilicon. This polysilicon layer has heavily doped polysilicon deposited by CVD. 19 / 26 19. In nMOS device, gate material could be .............. a. silicon b. polysilicon c. boron d. phosphorus Hint Transistor-transistor logic offers higher integration density and it became the first integrated circuit revolution. 20 / 26 20. Which provides higher integration density? a. switch transistor logic b. transistor buffer logic c. transistor transistor logic d. circuit level logic Hint Aluminium is the suitable material used for the circuit interconnection or connecting two layers. 21 / 26 21. Which is used for the interconnection? a. boron b. oxygen c. aluminium d. silicon 22 / 26 22. Heavily doped polysilicon is deposited using............... a. chemical vapour decomposition b. chemical vapour deposition c. chemical deposition d. dry deposition Hint p impurities are introduced as the crystal is grown. This increases the hole concentration in the device. 23 / 26 23. ................impurities are added to the wafer of the crystal. a. n impurities b. p impurities c. siicon d. Crystal Hint Gate minimization technique is used to find the simplest, smallest and effective implementation of the logic. 24 / 26 24. Gate minimization technique is used to simplify the logic. a. true b. false Hint Designers must simulate multiple fabrication process or use system level technique for dealing with effects of variation. 25 / 26 25. .....................is used to deal with effect of variation. a. chip level technique b. logic level technique c. switch level technique d. system level technique Hint SIlicon-di-oxide is a very good insulator so a very thin layer is required in the fabrication of MOS transistor. 26 / 26 26. SIlicon-di-oxide is a good insulator. a. true b. false Your score isThe average score is 5% LinkedIn Facebook Twitter VKontakte 0% Restart quiz